From b51a5ed1fab435c07b0767aa8bee4dda24991589 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Wed, 21 Jun 2023 06:55:18 -0700 Subject: [PATCH] Use both timers in `TIMG0` for embassy time driver when able (#609) * Use both timers in `TIMG0` for embassy time driver when able * Update CHANGELOG --- CHANGELOG.md | 1 + esp-hal-common/src/embassy/time_driver_timg.rs | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 50d0cc339..c9d9ae165 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -50,6 +50,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Move core interrupt handling from Flash to RAM for RISC-V chips (ESP32-H2, ESP32-C2, ESP32-C3, ESP32-C6) (#541) - Change LED pin to GPIO2 in ESP32 blinky example (#581) - Udpate ESP32-H2 and C6 ESP32-clocks and remove i2c_clock for all chips but ESP32 (#592) +- Use both timers in `TIMG0` for embassy time driver when able (#609) ### Fixed diff --git a/esp-hal-common/src/embassy/time_driver_timg.rs b/esp-hal-common/src/embassy/time_driver_timg.rs index 6f7869d5c..154bbfd44 100644 --- a/esp-hal-common/src/embassy/time_driver_timg.rs +++ b/esp-hal-common/src/embassy/time_driver_timg.rs @@ -9,7 +9,10 @@ use crate::{ timer::{Timer, Timer0}, }; +#[cfg(not(any(esp32, esp32s2, esp32s3)))] pub const ALARM_COUNT: usize = 1; +#[cfg(any(esp32, esp32s2, esp32s3))] +pub const ALARM_COUNT: usize = 2; pub type TimerInner = Timer0; pub type TimerType = Timer; @@ -49,16 +52,25 @@ impl EmbassyTimer { pub fn init(clocks: &Clocks, mut timer: TimerType) { use crate::{interrupt, interrupt::Priority}; - // set divider to get a 1mhz clock. abp (80mhz) / 80 = 1mhz... // TODO assert - // abp clock is the source and its at the correct speed for the divider + // set divider to get a 1mhz clock. APB (80mhz) / 80 = 1mhz... + // TODO: assert APB clock is the source and its at the correct speed for the + // divider timer.set_divider(clocks.apb_clock.to_MHz() as u16); interrupt::enable(peripherals::Interrupt::TG0_T0_LEVEL, Priority::max()).unwrap(); + #[cfg(any(esp32, esp32s2, esp32s3))] + interrupt::enable(peripherals::Interrupt::TG0_T1_LEVEL, Priority::max()).unwrap(); #[interrupt] fn TG0_T0_LEVEL() { DRIVER.on_interrupt(0); } + + #[cfg(any(esp32, esp32s2, esp32s3))] + #[interrupt] + fn TG0_T1_LEVEL() { + DRIVER.on_interrupt(1); + } } pub(crate) fn set_alarm(