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Address FIXME comments from #22

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This commit is contained in:
bjoernQ 2022-03-01 14:25:36 +01:00
parent 9bfe643f33
commit af9fecb8af
2 changed files with 7 additions and 32 deletions
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27
esp-hal-common/src/rtc_cntl.rs
View File

@ -12,36 +12,13 @@ impl RtcCntl {
/// Enable/disable write protection for WDT registers
fn set_wdt_write_protection(&mut self, enable: bool) {
let wkey = if enable { 0u32 } else { 0x50D8_3AA1 };
// FIXME: To be removed once the ESP32-S3 SVD
// register naming is aligned!
cfg_if::cfg_if! {
if #[cfg(any(feature = "esp32s3"))] {
let register = &self.rtc_cntl.rtc_wdtwprotect;
} else {
let register = &self.rtc_cntl.wdtwprotect;
}
}
register.write(|w| unsafe { w.bits(wkey) });
self.rtc_cntl.wdtwprotect.write(|w| unsafe { w.bits(wkey) });
}
/// Global switch for RTC_CNTL watchdog functionality
pub fn set_wdt_global_enable(&mut self, enable: bool) {
self.set_wdt_write_protection(false);
// FIXME: To be removed once the ESP32-S3 SVD
// register naming is aligned!
cfg_if::cfg_if! {
if #[cfg(any(feature = "esp32s3"))] {
let register = &self.rtc_cntl.rtc_wdtconfig0;
} else {
let register = &self.rtc_cntl.wdtconfig0;
}
}
register.modify(|_, w| w.wdt_en().bit(enable).wdt_flashboot_mod_en().clear_bit());
self.rtc_cntl.wdtconfig0.modify(|_, w| w.wdt_en().bit(enable).wdt_flashboot_mod_en().clear_bit());
self.set_wdt_write_protection(true);
}
}

12
esp32c3-hal/src/rtc_cntl.rs
View File

@ -13,7 +13,7 @@ impl RtcCntl {
self.set_swd_write_protection(false);
self.rtc_cntl
.rtc_swd_conf
.swd_conf
.write(|w| w.swd_auto_feed_en().bit(!enable));
self.set_swd_write_protection(true);
@ -23,7 +23,7 @@ impl RtcCntl {
let wkey = if enable { 0u32 } else { 0x8F1D_312A };
self.rtc_cntl
.rtc_swd_wprotect
.swd_wprotect
.write(|w| unsafe { w.swd_wkey().bits(wkey) });
}
@ -31,11 +31,9 @@ impl RtcCntl {
self.set_wdt_write_protection(false);
if !enable {
self.rtc_cntl.rtc_wdtconfig0.write(|w| unsafe { w.bits(0) });
self.rtc_cntl.wdtconfig0.write(|w| unsafe { w.bits(0) });
} else {
self.rtc_cntl
.rtc_wdtconfig0
.write(|w| w.wdt_en().bit(enable));
self.rtc_cntl.wdtconfig0.write(|w| w.wdt_en().bit(enable));
}
self.set_wdt_write_protection(true);
@ -45,7 +43,7 @@ impl RtcCntl {
let wkey = if enable { 0u32 } else { 0x50D8_3AA1 };
self.rtc_cntl
.rtc_wdtwprotect
.wdtwprotect
.write(|w| unsafe { w.wdt_wkey().bits(wkey) });
}
}