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Update esp32s2-ulp and esp32s3-ulp packages and address breaking changes

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This commit is contained in:
Jesse Braham 2023-11-27 11:54:29 +01:00 committed by Jesse Braham
parent b8f8828eb2
commit a54588d45b
3 changed files with 22 additions and 20 deletions
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16
esp-ulp-riscv-hal/Cargo.toml
View File

@ -22,17 +22,17 @@ categories = [
]
[dependencies]
embedded-hal = { version = "0.2.7", features = ["unproven"] }
procmacros = { package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
paste = "1.0.14"
esp32s2-ulp = { git = "https://github.com/esp-rs/esp-pacs", rev = "a7066cf", package = "esp32s2-ulp", optional = true }
esp32s3-ulp = { git = "https://github.com/esp-rs/esp-pacs", rev = "a7066cf", package = "esp32s3-ulp", optional = true }
embedded-hal = { version = "0.2.7", features = ["unproven"] }
procmacros = { package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
paste = "1.0.14"
esp32s2-ulp = { git = "https://github.com/esp-rs/esp-pacs", rev = "bb24582", optional = true }
esp32s3-ulp = { git = "https://github.com/esp-rs/esp-pacs", rev = "bb24582", optional = true }
[dev-dependencies]
panic-halt = "0.2.0"
panic-halt = "0.2.0"
[features]
default = []
debug = []
esp32s2 = [ "dep:esp32s2-ulp", "procmacros/esp32s2-ulp" ]
esp32s3 = [ "dep:esp32s3-ulp", "procmacros/esp32s3-ulp" ]
esp32s2 = ["dep:esp32s2-ulp", "procmacros/esp32s2-ulp"]
esp32s3 = ["dep:esp32s3-ulp", "procmacros/esp32s3-ulp"]

12
esp-ulp-riscv-hal/src/gpio.rs
View File

@ -42,13 +42,13 @@ pub struct GpioPin<MODE, const PIN: u8> {
impl<MODE, const PIN: u8> GpioPin<Input<MODE>, PIN> {
fn input_state(&self) -> bool {
unsafe { &*RTC_IO::PTR }.rtc_gpio_in.read().bits() >> PIN & 0x1 != 0
unsafe { &*RTC_IO::PTR }.rtc_gpio_in().read().bits() >> PIN & 0x1 != 0
}
}
impl<MODE, const PIN: u8> GpioPin<Output<MODE>, PIN> {
fn output_state(&self) -> bool {
unsafe { &*RTC_IO::PTR }.rtc_gpio_out.read().bits() >> PIN & 0x1 != 0
unsafe { &*RTC_IO::PTR }.rtc_gpio_out().read().bits() >> PIN & 0x1 != 0
}
fn set_output_low(&mut self) {
@ -56,24 +56,24 @@ impl<MODE, const PIN: u8> GpioPin<Output<MODE>, PIN> {
#[cfg(feature = "esp32s2")]
unsafe { &*RTC_IO::PTR }
.rtc_gpio_out_w1tc
.rtc_gpio_out_w1tc()
.write(|w| w.gpio_out_data_w1tc().variant(1 << PIN));
#[cfg(feature = "esp32s3")]
unsafe { &*RTC_IO::PTR }
.rtc_gpio_out_w1tc
.rtc_gpio_out_w1tc()
.write(|w| w.rtc_gpio_out_data_w1tc().variant(1 << PIN));
}
fn set_output_high(&mut self) {
#[cfg(feature = "esp32s2")]
unsafe { &*RTC_IO::PTR }
.rtc_gpio_out_w1ts
.rtc_gpio_out_w1ts()
.write(|w| w.gpio_out_data_w1ts().variant(1 << PIN));
#[cfg(feature = "esp32s3")]
unsafe { &*RTC_IO::PTR }
.rtc_gpio_out_w1ts
.rtc_gpio_out_w1ts()
.write(|w| w.rtc_gpio_out_data_w1ts().variant(1 << PIN));
}
}

14
esp-ulp-riscv-hal/src/lib.rs
View File

@ -60,11 +60,11 @@ unsafe extern "C" fn ulp_riscv_rescue_from_monitor() {
// TODO align naming in PACs
#[cfg(feature = "esp32s2")]
rtc_cntl
.cocpu_ctrl
.cocpu_ctrl()
.modify(|_, w| w.cocpu_done().clear_bit().cocpu_shut_reset_en().clear_bit());
#[cfg(feature = "esp32s3")]
rtc_cntl
.rtc_cocpu_ctrl
.rtc_cocpu_ctrl()
.modify(|_, w| w.cocpu_done().clear_bit().cocpu_shut_reset_en().clear_bit());
}
@ -77,19 +77,21 @@ unsafe extern "C" fn ulp_riscv_halt() {
#[cfg(feature = "esp32s2")]
{
rtc_cntl
.cocpu_ctrl
.cocpu_ctrl()
.modify(|_, w| w.cocpu_shut_2_clk_dis().variant(0x3f));
rtc_cntl.cocpu_ctrl.modify(|_, w| w.cocpu_done().set_bit());
rtc_cntl
.cocpu_ctrl()
.modify(|_, w| w.cocpu_done().set_bit());
}
#[cfg(feature = "esp32s3")]
{
rtc_cntl
.rtc_cocpu_ctrl
.rtc_cocpu_ctrl()
.modify(|_, w| w.cocpu_shut_2_clk_dis().variant(0x3f));
rtc_cntl
.rtc_cocpu_ctrl
.rtc_cocpu_ctrl()
.modify(|_, w| w.cocpu_done().set_bit());
}