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Fix RISC-V stack allocation (#988)

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Björn Quentin 2023-12-01 10:17:00 +01:00 committed by GitHub
parent 3d169bd80c
commit a40ea79277
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2 changed files with 3 additions and 1 deletions
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1
CHANGELOG.md
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@ -38,6 +38,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Async RMT channels can be used concurrently (#925) - Async RMT channels can be used concurrently (#925)
- Xtensa: Allow using `embassy-executor`'s thread-mode executor if neither `embassy-executor-thread`, nor `embassy-executor-interrupt` is enabled. (#937) - Xtensa: Allow using `embassy-executor`'s thread-mode executor if neither `embassy-executor-thread`, nor `embassy-executor-interrupt` is enabled. (#937)
- Uart Async: Improve interrupt handling and irq <--> future communication (#977) - Uart Async: Improve interrupt handling and irq <--> future communication (#977)
- RISC-V: Fix stack allocation (#988)
### Removed ### Removed

3
esp-riscv-rt/src/lib.rs
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@ -427,8 +427,9 @@ _abs_start:
// Allocate stack // Allocate stack
la sp, _stack_start la sp, _stack_start
lui t0, 16 li t0, 4 // make sure stack start is in RAM
sub sp, sp, t0 sub sp, sp, t0
andi sp, sp, -16 // Force 16-byte alignment
// Set frame pointer // Set frame pointer
add s0, sp, zero add s0, sp, zero