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Implement RTCIO pu/pd and hold control

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This commit is contained in:
Dániel Buga 2023-07-25 10:53:12 +02:00 committed by Jesse Braham
parent 92bda00296
commit a2ae6f37d1
5 changed files with 103 additions and 67 deletions
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1
CHANGELOG.md
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@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Add the `esp32c6-lp-hal` package (#714) - Add the `esp32c6-lp-hal` package (#714)
- Add GPIO (output) and delay functionality to `esp32c6-lp-hal` (#715) - Add GPIO (output) and delay functionality to `esp32c6-lp-hal` (#715)
- Implement RTCIO pullup, pulldown and hold control for Xtensa MCUs (#684)
### Changed ### Changed

45
esp-hal-common/src/gpio.rs
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@ -114,6 +114,12 @@ pub enum RtcFunction {
pub trait RTCPin: Pin { pub trait RTCPin: Pin {
fn rtc_number(&self) -> u8; fn rtc_number(&self) -> u8;
fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: RtcFunction); fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: RtcFunction);
fn rtcio_pad_hold(&mut self, enable: bool);
}
pub trait RTCPinWithResistors: RTCPin {
fn rtcio_pullup(&mut self, enable: bool);
fn rtcio_pulldown(&mut self, enable: bool);
} }
pub trait RTCInputPin: RTCPin {} pub trait RTCInputPin: RTCPin {}
@ -1443,11 +1449,9 @@ macro_rules! gpio {
#[macro_export] #[macro_export]
macro_rules! rtc_pins { macro_rules! rtc_pins {
( (
$pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat, $hold:ident $(, $rue:ident, $rde:ident)?
) => { ) => {
impl<MODE> crate::gpio::RTCPin for GpioPin<MODE, $pin_num> impl<MODE> crate::gpio::RTCPin for GpioPin<MODE, $pin_num>
where
Self: crate::gpio::GpioProperties,
{ {
fn rtc_number(&self) -> u8 { fn rtc_number(&self) -> u8 {
$rtc_pin $rtc_pin
@ -1468,14 +1472,45 @@ macro_rules! rtc_pins {
}); });
} }
} }
fn rtcio_pad_hold(&mut self, enable: bool) {
let rtc_ctrl = unsafe { &*crate::peripherals::RTC_CNTL::PTR };
#[cfg(esp32)]
rtc_ctrl.hold_force.modify(|_, w| w.$hold().bit(enable));
#[cfg(not(esp32))]
rtc_ctrl.pad_hold.modify(|_, w| w.$hold().bit(enable));
} }
}
$(
impl<MODE> crate::gpio::RTCPinWithResistors for GpioPin<MODE, $pin_num>
{
fn rtcio_pullup(&mut self, enable: bool) {
let rtcio = unsafe { &*crate::peripherals::RTC_IO::PTR };
paste::paste! {
rtcio.$pin_reg.modify(|_, w| w.$rue().bit([< enable >]));
}
}
fn rtcio_pulldown(&mut self, enable: bool) {
let rtcio = unsafe { &*crate::peripherals::RTC_IO::PTR };
paste::paste! {
rtcio.$pin_reg.modify(|_, w| w.$rde().bit([< enable >]));
}
}
}
)?
}; };
( (
$( ( $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat ) )+ $( ( $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat, $hold:ident $(, $rue:ident, $rde:ident)? ) )+
) => { ) => {
$( $(
crate::gpio::rtc_pins!($pin_num, $rtc_pin, $pin_reg, $prefix); crate::gpio::rtc_pins!($pin_num, $rtc_pin, $pin_reg, $prefix, $hold $(, $rue, $rde)?);
)+ )+
}; };
} }

36
esp-hal-common/src/soc/esp32/gpio.rs
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@ -763,24 +763,24 @@ crate::gpio::analog! {
} }
crate::gpio::rtc_pins! { crate::gpio::rtc_pins! {
(36, 0, sensor_pads, sense1_ ) (36, 0, sensor_pads, sense1_, sense1_hold_force )
(37, 1, sensor_pads, sense2_ ) (37, 1, sensor_pads, sense2_, sense2_hold_force )
(38, 2, sensor_pads, sense3_ ) (38, 2, sensor_pads, sense3_, sense3_hold_force )
(39, 3, sensor_pads, sense4_ ) (39, 3, sensor_pads, sense4_, sense4_hold_force )
(34, 4, adc_pad, adc1_ ) (34, 4, adc_pad, adc1_, adc1_hold_force )
(35, 5, adc_pad, adc2_ ) (35, 5, adc_pad, adc2_, adc2_hold_force )
(25, 6, pad_dac1, pdac1_ ) (25, 6, pad_dac1, pdac1_, pdac1_hold_force, pdac1_rue, pdac1_rde )
(26, 7, pad_dac2, pdac2_ ) (26, 7, pad_dac2, pdac2_, pdac2_hold_force, pdac2_rue, pdac2_rde )
(33, 8, xtal_32k_pad, x32n_ ) (33, 8, xtal_32k_pad, x32n_, x32n_hold_force, x32n_rue, x32n_rde )
(32, 9, xtal_32k_pad, x32p_ ) (32, 9, xtal_32k_pad, x32p_, x32p_hold_force, x32p_rue, x32p_rde )
(4, 10, touch_pad0, "") (4, 10, touch_pad0, "", touch_pad0_hold_force, rue, rde )
(0, 11, touch_pad1, "") (0, 11, touch_pad1, "", touch_pad1_hold_force, rue, rde )
(2, 12, touch_pad2, "") (2, 12, touch_pad2, "", touch_pad2_hold_force, rue, rde )
(15, 13, touch_pad3, "") (15, 13, touch_pad3, "", touch_pad3_hold_force, rue, rde )
(13, 14, touch_pad4, "") (13, 14, touch_pad4, "", touch_pad4_hold_force, rue, rde )
(12, 15, touch_pad5, "") (12, 15, touch_pad5, "", touch_pad5_hold_force, rue, rde )
(14, 16, touch_pad6, "") (14, 16, touch_pad6, "", touch_pad6_hold_force, rue, rde )
(27, 17, touch_pad7, "") (27, 17, touch_pad7, "", touch_pad7_hold_force, rue, rde )
} }
impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 { impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {

44
esp-hal-common/src/soc/esp32s2/gpio.rs
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@ -384,28 +384,28 @@ crate::gpio::analog! {
} }
crate::gpio::rtc_pins! { crate::gpio::rtc_pins! {
( 0, 0, touch_pad[0], "") ( 0, 0, touch_pad[0], "", touch_pad0_hold, rue, rde)
( 1, 1, touch_pad[1], "") ( 1, 1, touch_pad[1], "", touch_pad1_hold, rue, rde)
( 2, 2, touch_pad[2], "") ( 2, 2, touch_pad[2], "", touch_pad2_hold, rue, rde)
( 3, 3, touch_pad[3], "") ( 3, 3, touch_pad[3], "", touch_pad3_hold, rue, rde)
( 4, 4, touch_pad[4], "") ( 4, 4, touch_pad[4], "", touch_pad4_hold, rue, rde)
( 5, 5, touch_pad[5], "") ( 5, 5, touch_pad[5], "", touch_pad5_hold, rue, rde)
( 6, 6, touch_pad[6], "") ( 6, 6, touch_pad[6], "", touch_pad6_hold, rue, rde)
( 7, 7, touch_pad[7], "") ( 7, 7, touch_pad[7], "", touch_pad7_hold, rue, rde)
( 8, 8, touch_pad[8], "") ( 8, 8, touch_pad[8], "", touch_pad8_hold, rue, rde)
( 9, 9, touch_pad[9], "") ( 9, 9, touch_pad[9], "", touch_pad9_hold, rue, rde)
(10, 10, touch_pad[10], "") (10, 10, touch_pad[10], "", touch_pad10_hold, rue, rde)
(11, 11, touch_pad[11], "") (11, 11, touch_pad[11], "", touch_pad11_hold, rue, rde)
(12, 12, touch_pad[12], "") (12, 12, touch_pad[12], "", touch_pad12_hold, rue, rde)
(13, 13, touch_pad[13], "") (13, 13, touch_pad[13], "", touch_pad13_hold, rue, rde)
(14, 14, touch_pad[14], "") (14, 14, touch_pad[14], "", touch_pad14_hold, rue, rde)
(15, 15, xtal_32p_pad, x32p_) (15, 15, xtal_32p_pad, x32p_, x32p_hold, x32p_rue, x32p_rde)
(16, 16, xtal_32n_pad, x32n_) (16, 16, xtal_32n_pad, x32n_, x32n_hold, x32n_rue, x32n_rde)
(17, 17, pad_dac1, pdac1_) (17, 17, pad_dac1, pdac1_, pdac1_hold, pdac1_rue, pdac1_rde)
(18, 18, pad_dac2, pdac2_) (18, 18, pad_dac2, pdac2_, pdac2_hold, pdac2_rue, pdac2_rde)
(19, 19, rtc_pad19, "") (19, 19, rtc_pad19, "", pad19_hold, rue, rde)
(20, 20, rtc_pad20, "") (20, 20, rtc_pad20, "", pad20_hold, rue, rde)
(21, 21, rtc_pad21, "") (21, 21, rtc_pad21, "", pad21_hold, rue, rde)
} }
impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 { impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {

44
esp-hal-common/src/soc/esp32s3/gpio.rs
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@ -376,28 +376,28 @@ crate::gpio::analog! {
} }
crate::gpio::rtc_pins! { crate::gpio::rtc_pins! {
( 0, 0, touch_pad0, "") ( 0, 0, touch_pad0, "", touch_pad0_hold, rue, rde)
( 1, 1, touch_pad1, "") ( 1, 1, touch_pad1, "", touch_pad1_hold, rue, rde)
( 2, 2, touch_pad2, "") ( 2, 2, touch_pad2, "", touch_pad2_hold, rue, rde)
( 3, 3, touch_pad3, "") ( 3, 3, touch_pad3, "", touch_pad3_hold, rue, rde)
( 4, 4, touch_pad4, "") ( 4, 4, touch_pad4, "", touch_pad4_hold, rue, rde)
( 5, 5, touch_pad5, "") ( 5, 5, touch_pad5, "", touch_pad5_hold, rue, rde)
( 6, 6, touch_pad6, "") ( 6, 6, touch_pad6, "", touch_pad6_hold, rue, rde)
( 7, 7, touch_pad7, "") ( 7, 7, touch_pad7, "", touch_pad7_hold, rue, rde)
( 8, 8, touch_pad8, "") ( 8, 8, touch_pad8, "", touch_pad8_hold, rue, rde)
( 9, 9, touch_pad9, "") ( 9, 9, touch_pad9, "", touch_pad9_hold, rue, rde)
(10, 10, touch_pad10, "") (10, 10, touch_pad10, "", touch_pad10_hold, rue, rde)
(11, 11, touch_pad11, "") (11, 11, touch_pad11, "", touch_pad11_hold, rue, rde)
(12, 12, touch_pad12, "") (12, 12, touch_pad12, "", touch_pad12_hold, rue, rde)
(13, 13, touch_pad13, "") (13, 13, touch_pad13, "", touch_pad13_hold, rue, rde)
(14, 14, touch_pad14, "") (14, 14, touch_pad14, "", touch_pad14_hold, rue, rde)
(15, 15, xtal_32p_pad, x32p_) (15, 15, xtal_32p_pad, x32p_, x32p_hold, x32p_rue, x32p_rde)
(16, 16, xtal_32n_pad, x32n_) (16, 16, xtal_32n_pad, x32n_, x32n_hold, x32n_rue, x32n_rde)
(17, 17, pad_dac1, pdac1_) (17, 17, pad_dac1, pdac1_, pdac1_hold, pdac1_rue, pdac1_rde)
(18, 18, pad_dac2, pdac2_) (18, 18, pad_dac2, pdac2_, pdac2_hold, pdac2_rue, pdac2_rde)
(19, 19, rtc_pad19, "") (19, 19, rtc_pad19, "", pad19_hold, rue, rde)
(20, 20, rtc_pad20, "") (20, 20, rtc_pad20, "", pad20_hold, rue, rde)
(21, 21, rtc_pad21, "") (21, 21, rtc_pad21, "", pad21_hold, rue, rde)
} }
// Whilst the S3 is a dual core chip, it shares the enable registers between // Whilst the S3 is a dual core chip, it shares the enable registers between