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update pac (#1357)

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Zgarbul Andrey 2024-03-30 01:51:48 +03:00 committed by GitHub
parent 7d5372f57d
commit 9f035d40a9
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GPG Key ID: B5690EEEBB952194
27 changed files with 510 additions and 579 deletions
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1
esp-hal/CHANGELOG.md
View File

@ -40,6 +40,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- All `Instance` traits are now sealed, and can no longer be implemented for arbitrary types (#1346)
- DMA channels can/have to be explicitly created for async or blocking drivers, added `set_interrupt_handler` to DMA channels, SPI, I2S, PARL_IO, don't enable interrupts on startup for DMA, I2S, PARL_IO, GPIO (#1300)
- UART: Rework `change_baud` so it is possible to set baud rate even after instantiation (#1350)
- Update `pac`s with removed suffixes in `int` field names. Use `W1TC` for `int_clr`
### Removed

16
esp-hal/Cargo.toml
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@ -52,14 +52,14 @@ xtensa-lx = { version = "0.9.0", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.7.0", optional = true, path = "../esp-riscv-rt" }

8
esp-hal/src/analog/adc/riscv.rs
View File

@ -288,7 +288,7 @@ impl RegisterAccess for crate::peripherals::ADC1 {
fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };
sar_adc.int_raw().read().apb_saradc1_done_int_raw().bit()
sar_adc.int_raw().read().apb_saradc1_done().bit()
}
fn read_data() -> u16 {
@ -303,7 +303,7 @@ impl RegisterAccess for crate::peripherals::ADC1 {
// Clear ADC1 sampling done interrupt bit
sar_adc
.int_clr()
.write(|w| w.apb_saradc1_done_int_clr().set_bit());
.write(|w| w.apb_saradc1_done().clear_bit_by_one());
// Disable ADC sampling
sar_adc
@ -399,7 +399,7 @@ impl RegisterAccess for crate::peripherals::ADC2 {
fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };
sar_adc.int_raw().read().apb_saradc2_done_int_raw().bit()
sar_adc.int_raw().read().apb_saradc2_done().bit()
}
fn read_data() -> u16 {
@ -413,7 +413,7 @@ impl RegisterAccess for crate::peripherals::ADC2 {
sar_adc
.int_clr()
.write(|w| w.apb_saradc2_done_int_clr().set_bit());
.write(|w| w.apb_saradc2_done().clear_bit_by_one());
sar_adc
.onetime_sample()

8
esp-hal/src/analog/adc/xtensa.rs
View File

@ -347,10 +347,10 @@ impl RegisterAccess for crate::peripherals::ADC1 {
cfg_if::cfg_if! {
if #[cfg(esp32s2)] {
adc.int_clr()
.write(|w| w.adc1_done_int_clr().set_bit());
.write(|w| w.adc1_done().clear_bit_by_one());
} else {
adc.int_clr()
.write(|w| w.apb_saradc1_done_int_clr().set_bit());
.write(|w| w.apb_saradc1_done().clear_bit_by_one());
}
}
@ -486,10 +486,10 @@ impl RegisterAccess for crate::peripherals::ADC2 {
cfg_if::cfg_if! {
if #[cfg(esp32s2)] {
adc.int_clr()
.write(|w| w.adc2_done_int_clr().set_bit());
.write(|w| w.adc2_done().clear_bit_by_one());
} else {
adc.int_clr()
.write(|w| w.apb_saradc2_done_int_clr().set_bit());
.write(|w| w.apb_saradc2_done().clear_bit_by_one());
}
}

72
esp-hal/src/dma/gdma.rs
View File

@ -105,24 +105,24 @@ impl<const N: u8> RegisterAccess for Channel<N> {
fn clear_out_interrupts() {
#[cfg(not(esp32s3))]
Self::out_int().clr().write(|w| {
w.out_eof().set_bit();
w.out_dscr_err().set_bit();
w.out_done().set_bit();
w.out_total_eof().set_bit();
w.outfifo_ovf().set_bit();
w.outfifo_udf().set_bit()
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf().clear_bit_by_one();
w.outfifo_udf().clear_bit_by_one()
});
#[cfg(esp32s3)]
Self::out_int().clr().write(|w| {
w.out_eof().set_bit();
w.out_dscr_err().set_bit();
w.out_done().set_bit();
w.out_total_eof().set_bit();
w.outfifo_ovf_l1().set_bit();
w.outfifo_ovf_l3().set_bit();
w.outfifo_udf_l1().set_bit();
w.outfifo_udf_l3().set_bit()
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf_l1().clear_bit_by_one();
w.outfifo_ovf_l3().clear_bit_by_one();
w.outfifo_udf_l1().clear_bit_by_one();
w.outfifo_udf_l3().clear_bit_by_one()
});
}
@ -155,7 +155,9 @@ impl<const N: u8> RegisterAccess for Channel<N> {
}
fn clear_ch_out_done() {
Self::out_int().clr().write(|w| w.out_done().set_bit());
Self::out_int()
.clr()
.write(|w| w.out_done().clear_bit_by_one());
}
fn is_ch_out_done_set() -> bool {
@ -193,7 +195,9 @@ impl<const N: u8> RegisterAccess for Channel<N> {
}
fn reset_out_eof_interrupt() {
Self::out_int().clr().write(|w| w.out_eof().set_bit());
Self::out_int()
.clr()
.write(|w| w.out_eof().clear_bit_by_one());
}
fn set_in_burstmode(burst_mode: bool) {
@ -214,26 +218,26 @@ impl<const N: u8> RegisterAccess for Channel<N> {
fn clear_in_interrupts() {
#[cfg(not(esp32s3))]
Self::in_int().clr().write(|w| {
w.in_suc_eof().set_bit();
w.in_err_eof().set_bit();
w.in_dscr_err().set_bit();
w.in_dscr_empty().set_bit();
w.in_done().set_bit();
w.infifo_ovf().set_bit();
w.infifo_udf().set_bit()
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf().clear_bit_by_one();
w.infifo_udf().clear_bit_by_one()
});
#[cfg(esp32s3)]
Self::in_int().clr().write(|w| {
w.in_suc_eof().set_bit();
w.in_err_eof().set_bit();
w.in_dscr_err().set_bit();
w.in_dscr_empty().set_bit();
w.in_done().set_bit();
w.infifo_ovf_l1().set_bit();
w.infifo_ovf_l3().set_bit();
w.infifo_udf_l1().set_bit();
w.infifo_udf_l3().set_bit()
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf_l1().clear_bit_by_one();
w.infifo_ovf_l3().clear_bit_by_one();
w.infifo_udf_l1().clear_bit_by_one();
w.infifo_udf_l3().clear_bit_by_one()
});
}
@ -316,7 +320,9 @@ impl<const N: u8> RegisterAccess for Channel<N> {
}
fn clear_ch_in_done() {
Self::in_int().clr().write(|w| w.in_done().set_bit());
Self::in_int()
.clr()
.write(|w| w.in_done().clear_bit_by_one());
}
fn is_ch_in_done_set() -> bool {

164
esp-hal/src/dma/pdma.rs
View File

@ -78,14 +78,14 @@ macro_rules! ImplSpiChannel {
fn clear_out_interrupts() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_clr().write(|w| {
w.out_done_int_clr()
.set_bit()
.out_eof_int_clr()
.set_bit()
.out_total_eof_int_clr()
.set_bit()
.outlink_dscr_error_int_clr()
.set_bit()
w.out_done()
.clear_bit_by_one()
.out_eof()
.clear_bit_by_one()
.out_total_eof()
.clear_bit_by_one()
.outlink_dscr_error()
.clear_bit_by_one()
});
}
@ -103,7 +103,7 @@ macro_rules! ImplSpiChannel {
fn has_out_descriptor_error() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().outlink_dscr_error_int_raw().bit()
spi.dma_int_raw().read().outlink_dscr_error().bit()
}
fn set_out_peripheral(_peripheral: u8) {
@ -117,33 +117,33 @@ macro_rules! ImplSpiChannel {
fn clear_ch_out_done() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_clr().write(|w| w.out_done_int_clr().set_bit());
spi.dma_int_clr().write(|w| w.out_done().clear_bit_by_one());
}
fn is_ch_out_done_set() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().out_done_int_raw().bit()
spi.dma_int_raw().read().out_done().bit()
}
fn listen_ch_out_done() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.out_done_int_ena().set_bit());
spi.dma_int_ena().modify(|_, w| w.out_done().set_bit());
}
fn unlisten_ch_out_done() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.out_done_int_ena().clear_bit());
spi.dma_int_ena().modify(|_, w| w.out_done().clear_bit());
}
fn is_listening_ch_out_done() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().read().out_done_int_ena().bit()
spi.dma_int_ena().read().out_done().bit()
}
fn is_out_done() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
// FIXME this should be out_total_eof_int_raw? but on esp32 this interrupt doesn't seem to fire
spi.dma_int_raw().read().out_eof_int_raw().bit()
spi.dma_int_raw().read().out_eof().bit()
}
fn last_out_dscr_address() -> usize {
@ -153,14 +153,14 @@ macro_rules! ImplSpiChannel {
fn is_out_eof_interrupt_set() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().out_eof_int_raw().bit()
spi.dma_int_raw().read().out_eof().bit()
}
fn reset_out_eof_interrupt() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_clr().write(|w| {
w.out_eof_int_clr()
.set_bit()
w.out_eof()
.clear_bit_by_one()
});
}
@ -175,14 +175,14 @@ macro_rules! ImplSpiChannel {
fn clear_in_interrupts() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_clr().write(|w| {
w.in_done_int_clr()
.set_bit()
.in_err_eof_int_clr()
.set_bit()
.in_suc_eof_int_clr()
.set_bit()
.inlink_dscr_error_int_clr()
.set_bit()
w.in_done()
.clear_bit_by_one()
.in_err_eof()
.clear_bit_by_one()
.in_suc_eof()
.clear_bit_by_one()
.inlink_dscr_error()
.clear_bit_by_one()
});
}
@ -200,17 +200,17 @@ macro_rules! ImplSpiChannel {
fn has_in_descriptor_error() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().inlink_dscr_error_int_raw().bit()
spi.dma_int_raw().read().inlink_dscr_error().bit()
}
fn has_in_descriptor_error_dscr_empty() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().inlink_dscr_empty_int_raw().bit()
spi.dma_int_raw().read().inlink_dscr_empty().bit()
}
fn has_in_descriptor_error_err_eof() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().in_err_eof_int_raw().bit()
spi.dma_int_raw().read().in_err_eof().bit()
}
fn set_in_peripheral(_peripheral: u8) {
@ -224,7 +224,7 @@ macro_rules! ImplSpiChannel {
fn is_in_done() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().in_done_int_raw().bit()
spi.dma_int_raw().read().in_done().bit()
}
fn last_in_dscr_address() -> usize {
@ -234,57 +234,57 @@ macro_rules! ImplSpiChannel {
fn is_listening_in_eof() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().read().in_suc_eof_int_ena().bit_is_set()
spi.dma_int_ena().read().in_suc_eof().bit_is_set()
}
fn is_listening_out_eof() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().read().out_total_eof_int_ena().bit_is_set()
spi.dma_int_ena().read().out_total_eof().bit_is_set()
}
fn listen_in_eof() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.in_suc_eof_int_ena().set_bit());
spi.dma_int_ena().modify(|_, w| w.in_suc_eof().set_bit());
}
fn listen_out_eof() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.out_total_eof_int_ena().set_bit());
spi.dma_int_ena().modify(|_, w| w.out_total_eof().set_bit());
}
fn unlisten_in_eof() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.in_suc_eof_int_ena().clear_bit());
spi.dma_int_ena().modify(|_, w| w.in_suc_eof().clear_bit());
}
fn unlisten_out_eof() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.out_total_eof_int_ena().clear_bit());
spi.dma_int_ena().modify(|_, w| w.out_total_eof().clear_bit());
}
fn listen_ch_in_done(){
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.in_done_int_ena().set_bit());
spi.dma_int_ena().modify(|_, w| w.in_done().set_bit());
}
fn clear_ch_in_done(){
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_clr().write(|w| w.in_done_int_clr().set_bit());
spi.dma_int_clr().write(|w| w.in_done().clear_bit_by_one());
}
fn is_ch_in_done_set() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_raw().read().in_done_int_raw().bit()
spi.dma_int_raw().read().in_done().bit()
}
fn unlisten_ch_in_done() {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().modify(|_, w| w.in_done_int_ena().clear_bit());
spi.dma_int_ena().modify(|_, w| w.in_done().clear_bit());
}
fn is_listening_ch_in_done() -> bool {
let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
spi.dma_int_ena().read().in_done_int_ena().bit()
spi.dma_int_ena().read().in_done().bit()
}
}
@ -409,14 +409,14 @@ macro_rules! ImplI2sChannel {
fn clear_out_interrupts() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_clr().write(|w| {
w.out_done_int_clr()
.set_bit()
.out_eof_int_clr()
.set_bit()
.out_total_eof_int_clr()
.set_bit()
.out_dscr_err_int_clr()
.set_bit()
w.out_done()
.clear_bit_by_one()
.out_eof()
.clear_bit_by_one()
.out_total_eof()
.clear_bit_by_one()
.out_dscr_err()
.clear_bit_by_one()
});
}
@ -434,7 +434,7 @@ macro_rules! ImplI2sChannel {
fn has_out_descriptor_error() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().out_dscr_err_int_raw().bit()
reg_block.int_raw().read().out_dscr_err().bit()
}
fn set_out_peripheral(_peripheral: u8) {
@ -448,32 +448,32 @@ macro_rules! ImplI2sChannel {
fn clear_ch_out_done() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_clr().write(|w| w.out_done_int_clr().set_bit());
reg_block.int_clr().write(|w| w.out_done().clear_bit_by_one());
}
fn is_ch_out_done_set() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().out_done_int_raw().bit()
reg_block.int_raw().read().out_done().bit()
}
fn listen_ch_out_done() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_, w| w.out_done_int_ena().set_bit());
reg_block.int_ena().modify(|_, w| w.out_done().set_bit());
}
fn unlisten_ch_out_done() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_, w| w.out_done_int_ena().clear_bit());
reg_block.int_ena().modify(|_, w| w.out_done().clear_bit());
}
fn is_listening_ch_out_done() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().read().out_done_int_ena().bit()
reg_block.int_ena().read().out_done().bit()
}
fn is_out_done() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().out_eof_int_raw().bit()
reg_block.int_raw().read().out_eof().bit()
}
fn last_out_dscr_address() -> usize {
@ -483,14 +483,14 @@ macro_rules! ImplI2sChannel {
fn is_out_eof_interrupt_set() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().out_eof_int_raw().bit()
reg_block.int_raw().read().out_eof().bit()
}
fn reset_out_eof_interrupt() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_clr().write(|w| {
w.out_eof_int_clr()
.set_bit()
w.out_eof()
.clear_bit_by_one()
});
}
@ -505,14 +505,14 @@ macro_rules! ImplI2sChannel {
fn clear_in_interrupts() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_clr().write(|w| {
w.in_done_int_clr()
.set_bit()
.in_err_eof_int_clr()
.set_bit()
.in_suc_eof_int_clr()
.set_bit()
.in_dscr_err_int_clr()
.set_bit()
w.in_done()
.clear_bit_by_one()
.in_err_eof()
.clear_bit_by_one()
.in_suc_eof()
.clear_bit_by_one()
.in_dscr_err()
.clear_bit_by_one()
});
}
@ -530,17 +530,17 @@ macro_rules! ImplI2sChannel {
fn has_in_descriptor_error() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().in_dscr_err_int_raw().bit()
reg_block.int_raw().read().in_dscr_err().bit()
}
fn has_in_descriptor_error_dscr_empty() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().in_dscr_empty_int_raw().bit()
reg_block.int_raw().read().in_dscr_empty().bit()
}
fn has_in_descriptor_error_err_eof() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().in_err_eof_int_raw().bit()
reg_block.int_raw().read().in_err_eof().bit()
}
fn set_in_peripheral(_peripheral: u8) {
@ -554,7 +554,7 @@ macro_rules! ImplI2sChannel {
fn is_in_done() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().in_done_int_raw().bit()
reg_block.int_raw().read().in_done().bit()
}
fn last_in_dscr_address() -> usize {
@ -564,57 +564,57 @@ macro_rules! ImplI2sChannel {
fn is_listening_in_eof() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().read().in_suc_eof_int_ena().bit()
reg_block.int_ena().read().in_suc_eof().bit()
}
fn is_listening_out_eof() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().read().out_eof_int_ena().bit()
reg_block.int_ena().read().out_eof().bit()
}
fn listen_in_eof() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_,w| w.in_suc_eof_int_ena().set_bit() );
reg_block.int_ena().modify(|_,w| w.in_suc_eof().set_bit() );
}
fn listen_out_eof() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_,w| w.out_eof_int_ena().set_bit() );
reg_block.int_ena().modify(|_,w| w.out_eof().set_bit() );
}
fn unlisten_in_eof() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_,w| w.in_suc_eof_int_ena().clear_bit() );
reg_block.int_ena().modify(|_,w| w.in_suc_eof().clear_bit() );
}
fn unlisten_out_eof() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_,w| w.out_eof_int_ena().clear_bit() );
reg_block.int_ena().modify(|_,w| w.out_eof().clear_bit() );
}
fn listen_ch_in_done(){
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_, w| w.in_done_int_ena().set_bit());
reg_block.int_ena().modify(|_, w| w.in_done().set_bit());
}
fn clear_ch_in_done(){
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_clr().write(|w| w.in_done_int_clr().set_bit());
reg_block.int_clr().write(|w| w.in_done().clear_bit_by_one());
}
fn is_ch_in_done_set() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_raw().read().in_done_int_raw().bit()
reg_block.int_raw().read().in_done().bit()
}
fn unlisten_ch_in_done() {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().modify(|_, w| w.in_done_int_ena().clear_bit());
reg_block.int_ena().modify(|_, w| w.in_done().clear_bit());
}
fn is_listening_ch_in_done() -> bool {
let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
reg_block.int_ena().read().in_done_int_ena().bit()
reg_block.int_ena().read().in_done().bit()
}
}

72
esp-hal/src/i2c.rs
View File

@ -380,10 +380,10 @@ mod asynch {
.register_block()
.int_ena()
.modify(|_, w| match event {
Event::EndDetect => w.end_detect_int_ena().set_bit(),
Event::TxComplete => w.trans_complete_int_ena().set_bit(),
Event::EndDetect => w.end_detect().set_bit(),
Event::TxComplete => w.trans_complete().set_bit(),
#[cfg(not(any(esp32, esp32s2)))]
Event::TxFifoWatermark => w.txfifo_wm_int_ena().set_bit(),
Event::TxFifoWatermark => w.txfifo_wm().set_bit(),
});
Self { event, instance }
@ -393,10 +393,10 @@ mod asynch {
let r = self.instance.register_block().int_ena().read();
match self.event {
Event::EndDetect => r.end_detect_int_ena().bit_is_clear(),
Event::TxComplete => r.trans_complete_int_ena().bit_is_clear(),
Event::EndDetect => r.end_detect().bit_is_clear(),
Event::TxComplete => r.trans_complete().bit_is_clear(),
#[cfg(not(any(esp32, esp32s2)))]
Event::TxFifoWatermark => r.txfifo_wm_int_ena().bit_is_clear(),
Event::TxFifoWatermark => r.txfifo_wm().bit_is_clear(),
}
}
}
@ -539,7 +539,7 @@ mod asynch {
self.peripheral
.register_block()
.int_clr()
.write(|w| w.txfifo_wm_int_clr().set_bit());
.write(|w| w.txfifo_wm().clear_bit_by_one());
I2cFuture::new(Event::TxFifoWatermark, self.inner()).await;
@ -608,17 +608,12 @@ mod asynch {
fn I2C_EXT0() {
unsafe { &*crate::peripherals::I2C0::PTR }
.int_ena()
.modify(|_, w| {
w.end_detect_int_ena()
.clear_bit()
.trans_complete_int_ena()
.clear_bit()
});
.modify(|_, w| w.end_detect().clear_bit().trans_complete().clear_bit());
#[cfg(not(any(esp32, esp32s2)))]
unsafe { &*crate::peripherals::I2C0::PTR }
.int_ena()
.modify(|_, w| w.txfifo_wm_int_ena().clear_bit());
.modify(|_, w| w.txfifo_wm().clear_bit());
WAKERS[0].wake();
}
@ -628,17 +623,12 @@ mod asynch {
fn I2C_EXT1() {
unsafe { &*crate::peripherals::I2C1::PTR }
.int_ena()
.modify(|_, w| {
w.end_detect_int_ena()
.clear_bit()
.trans_complete_int_ena()
.clear_bit()
});
.modify(|_, w| w.end_detect().clear_bit().trans_complete().clear_bit());
#[cfg(not(any(esp32, esp32s2)))]
unsafe { &*crate::peripherals::I2C0::PTR }
.int_ena()
.modify(|_, w| w.txfifo_wm_int_ena().clear_bit());
.modify(|_, w| w.txfifo_wm().clear_bit());
WAKERS[1].wake();
}
@ -1272,9 +1262,7 @@ pub trait Instance: crate::private::Sealed {
// Handle completion cases
// A full transmission was completed
if interrupts.trans_complete_int_raw().bit_is_set()
|| interrupts.end_detect_int_raw().bit_is_set()
{
if interrupts.trans_complete().bit_is_set() || interrupts.end_detect().bit_is_set() {
break;
}
}
@ -1295,29 +1283,29 @@ pub trait Instance: crate::private::Sealed {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
// Handle error cases
if interrupts.time_out_int_raw().bit_is_set() {
if interrupts.time_out().bit_is_set() {
self.reset();
return Err(Error::TimeOut);
} else if interrupts.ack_err_int_raw().bit_is_set() {
} else if interrupts.ack_err().bit_is_set() {
self.reset();
return Err(Error::AckCheckFailed);
} else if interrupts.arbitration_lost_int_raw().bit_is_set() {
} else if interrupts.arbitration_lost().bit_is_set() {
self.reset();
return Err(Error::ArbitrationLost);
}
}
else {
// Handle error cases
if interrupts.time_out_int_raw().bit_is_set() {
if interrupts.time_out().bit_is_set() {
self.reset();
return Err(Error::TimeOut);
} else if interrupts.nack_int_raw().bit_is_set() {
} else if interrupts.nack().bit_is_set() {
self.reset();
return Err(Error::AckCheckFailed);
} else if interrupts.arbitration_lost_int_raw().bit_is_set() {
} else if interrupts.arbitration_lost().bit_is_set() {
self.reset();
return Err(Error::ArbitrationLost);
} else if interrupts.trans_complete_int_raw().bit_is_set() && self.register_block().sr().read().resp_rec().bit_is_clear() {
} else if interrupts.trans_complete().bit_is_set() && self.register_block().sr().read().resp_rec().bit_is_clear() {
self.reset();
return Err(Error::AckCheckFailed);
}
@ -1351,7 +1339,7 @@ pub trait Instance: crate::private::Sealed {
.register_block()
.int_raw()
.read()
.txfifo_ovf_int_raw()
.txfifo_ovf()
.bit_is_set()
{
write_fifo(self.register_block(), bytes[index]);
@ -1361,13 +1349,13 @@ pub trait Instance: crate::private::Sealed {
.register_block()
.int_raw()
.read()
.txfifo_ovf_int_raw()
.txfifo_ovf()
.bit_is_set()
{
index -= 1;
self.register_block()
.int_clr()
.write(|w| w.txfifo_ovf_int_clr().set_bit());
.write(|w| w.txfifo_ovf().clear_bit_by_one());
}
index
}
@ -1382,19 +1370,19 @@ pub trait Instance: crate::private::Sealed {
.register_block()
.int_raw()
.read()
.txfifo_wm_int_raw()
.txfifo_wm()
.bit_is_set()
{}
self.register_block()
.int_clr()
.write(|w| w.txfifo_wm_int_clr().set_bit());
.write(|w| w.txfifo_wm().clear_bit_by_one());
while !self
.register_block()
.int_raw()
.read()
.txfifo_wm_int_raw()
.txfifo_wm()
.bit_is_set()
{}
@ -1468,10 +1456,10 @@ pub trait Instance: crate::private::Sealed {
.modify(|_, w| w.tx_fifo_rst().clear_bit().rx_fifo_rst().clear_bit());
self.register_block().int_clr().write(|w| {
w.rxfifo_wm_int_clr()
.set_bit()
.txfifo_wm_int_clr()
.set_bit()
w.rxfifo_wm()
.clear_bit_by_one()
.txfifo_wm()
.clear_bit_by_one()
});
self.update_config();
@ -1500,7 +1488,7 @@ pub trait Instance: crate::private::Sealed {
self.register_block()
.int_clr()
.write(|w| w.rxfifo_full_int_clr().set_bit());
.write(|w| w.rxfifo_full().clear_bit_by_one());
}
/// Send data bytes from the `bytes` array to a target slave with the

150
esp-hal/src/i2s.rs
View File

@ -1106,12 +1106,12 @@ mod private {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::TxHung => reg_block
.int_ena()
.modify(|_, w| w.tx_hung_int_ena().set_bit()),
I2sInterrupt::RxHung => reg_block
.int_ena()
.modify(|_, w| w.rx_hung_int_ena().set_bit()),
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
}
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().set_bit())
}
}
}
}
@ -1121,12 +1121,12 @@ mod private {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::TxHung => reg_block
.int_ena()
.modify(|_, w| w.tx_hung_int_ena().clear_bit()),
I2sInterrupt::RxHung => reg_block
.int_ena()
.modify(|_, w| w.rx_hung_int_ena().clear_bit()),
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
}
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().clear_bit())
}
}
}
}
@ -1136,10 +1136,10 @@ mod private {
let reg_block = Self::register_block();
let ints = reg_block.int_st().read();
if ints.tx_hung_int_st().bit() {
if ints.tx_hung().bit() {
res.insert(I2sInterrupt::TxHung);
}
if ints.rx_hung_int_st().bit() {
if ints.rx_hung().bit() {
res.insert(I2sInterrupt::RxHung);
}
@ -1151,12 +1151,12 @@ mod private {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::TxHung => {
reg_block.int_clr().write(|w| w.tx_hung_int_clr().set_bit())
}
I2sInterrupt::RxHung => {
reg_block.int_clr().write(|w| w.rx_hung_int_clr().set_bit())
}
I2sInterrupt::TxHung => reg_block
.int_clr()
.write(|w| w.tx_hung().clear_bit_by_one()),
I2sInterrupt::RxHung => reg_block
.int_clr()
.write(|w| w.rx_hung().clear_bit_by_one()),
}
}
}
@ -1283,10 +1283,10 @@ mod private {
i2s.lc_conf().modify(|_, w| w.out_rst().clear_bit());
i2s.int_clr().write(|w| {
w.out_done_int_clr()
.set_bit()
.out_total_eof_int_clr()
.set_bit()
w.out_done()
.clear_bit_by_one()
.out_total_eof()
.clear_bit_by_one()
});
}
@ -1319,14 +1319,18 @@ mod private {
i2s.lc_conf().modify(|_, w| w.in_rst().set_bit());
i2s.lc_conf().modify(|_, w| w.in_rst().clear_bit());
i2s.int_clr()
.write(|w| w.in_done_int_clr().set_bit().in_suc_eof_int_clr().set_bit());
i2s.int_clr().write(|w| {
w.in_done()
.clear_bit_by_one()
.in_suc_eof()
.clear_bit_by_one()
});
}
fn rx_start(len: usize) {
let i2s = Self::register_block();
i2s.int_clr().write(|w| w.in_suc_eof_int_clr().set_bit());
i2s.int_clr().write(|w| w.in_suc_eof().clear_bit_by_one());
#[cfg(not(esp32))]
i2s.rxeof_num()
@ -1342,11 +1346,11 @@ mod private {
fn wait_for_rx_done() {
let i2s = Self::register_block();
while i2s.int_raw().read().in_suc_eof_int_raw().bit_is_clear() {
while i2s.int_raw().read().in_suc_eof().bit_is_clear() {
// wait
}
i2s.int_clr().write(|w| w.in_suc_eof_int_clr().set_bit());
i2s.int_clr().write(|w| w.in_suc_eof().clear_bit_by_one());
}
}
@ -1359,18 +1363,18 @@ mod private {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::TxHung => reg_block
.int_ena()
.modify(|_, w| w.tx_hung_int_ena().set_bit()),
I2sInterrupt::RxHung => reg_block
.int_ena()
.modify(|_, w| w.rx_hung_int_ena().set_bit()),
I2sInterrupt::TxDone => reg_block
.int_ena()
.modify(|_, w| w.tx_done_int_ena().set_bit()),
I2sInterrupt::RxDone => reg_block
.int_ena()
.modify(|_, w| w.rx_done_int_ena().set_bit()),
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
}
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().set_bit())
}
I2sInterrupt::TxDone => {
reg_block.int_ena().modify(|_, w| w.tx_done().set_bit())
}
I2sInterrupt::RxDone => {
reg_block.int_ena().modify(|_, w| w.rx_done().set_bit())
}
}
}
}
@ -1380,18 +1384,18 @@ mod private {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::TxHung => reg_block
.int_ena()
.modify(|_, w| w.tx_hung_int_ena().clear_bit()),
I2sInterrupt::RxHung => reg_block
.int_ena()
.modify(|_, w| w.rx_hung_int_ena().clear_bit()),
I2sInterrupt::TxDone => reg_block
.int_ena()
.modify(|_, w| w.tx_done_int_ena().clear_bit()),
I2sInterrupt::RxDone => reg_block
.int_ena()
.modify(|_, w| w.rx_done_int_ena().clear_bit()),
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
}
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().clear_bit())
}
I2sInterrupt::TxDone => {
reg_block.int_ena().modify(|_, w| w.tx_done().clear_bit())
}
I2sInterrupt::RxDone => {
reg_block.int_ena().modify(|_, w| w.rx_done().clear_bit())
}
}
}
}
@ -1401,16 +1405,16 @@ mod private {
let reg_block = Self::register_block();
let ints = reg_block.int_st().read();
if ints.tx_hung_int_st().bit() {
if ints.tx_hung().bit() {
res.insert(I2sInterrupt::TxHung);
}
if ints.rx_hung_int_st().bit() {
if ints.rx_hung().bit() {
res.insert(I2sInterrupt::RxHung);
}
if ints.tx_done_int_st().bit() {
if ints.tx_done().bit() {
res.insert(I2sInterrupt::TxDone);
}
if ints.rx_done_int_st().bit() {
if ints.rx_done().bit() {
res.insert(I2sInterrupt::RxDone);
}
@ -1422,18 +1426,18 @@ mod private {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::TxHung => {
reg_block.int_clr().write(|w| w.tx_hung_int_clr().set_bit())
}
I2sInterrupt::RxHung => {
reg_block.int_clr().write(|w| w.rx_hung_int_clr().set_bit())
}
I2sInterrupt::TxDone => {
reg_block.int_clr().write(|w| w.tx_done_int_clr().set_bit())
}
I2sInterrupt::RxDone => {
reg_block.int_clr().write(|w| w.rx_done_int_clr().set_bit())
}
I2sInterrupt::TxHung => reg_block
.int_clr()
.write(|w| w.tx_hung().clear_bit_by_one()),
I2sInterrupt::RxHung => reg_block
.int_clr()
.write(|w| w.rx_hung().clear_bit_by_one()),
I2sInterrupt::TxDone => reg_block
.int_clr()
.write(|w| w.tx_done().clear_bit_by_one()),
I2sInterrupt::RxDone => reg_block
.int_clr()
.write(|w| w.rx_done().clear_bit_by_one()),
}
}
}
@ -1818,7 +1822,7 @@ mod private {
.modify(|_, w| w.tx_reset().clear_bit().tx_fifo_reset().clear_bit());
i2s.int_clr()
.write(|w| w.tx_done_int_clr().set_bit().tx_hung_int_clr().set_bit());
.write(|w| w.tx_done().clear_bit_by_one().tx_hung().clear_bit_by_one());
}
fn tx_start() {
@ -1848,7 +1852,7 @@ mod private {
.modify(|_, w| w.rx_reset().clear_bit().rx_fifo_reset().clear_bit());
i2s.int_clr()
.write(|w| w.rx_done_int_clr().set_bit().rx_hung_int_clr().set_bit());
.write(|w| w.rx_done().clear_bit_by_one().rx_hung().clear_bit_by_one());
}
fn rx_start(len: usize) {
@ -1860,11 +1864,11 @@ mod private {
fn wait_for_rx_done() {
let i2s = Self::register_block();
while i2s.int_raw().read().rx_done_int_raw().bit_is_clear() {
while i2s.int_raw().read().rx_done().bit_is_clear() {
// wait
}
i2s.int_clr().write(|w| w.rx_done_int_clr().set_bit());
i2s.int_clr().write(|w| w.rx_done().clear_bit_by_one());
}
}

10
esp-hal/src/ledc/channel.rs
View File

@ -549,7 +549,7 @@ macro_rules! set_duty_fade {
.write(|w| unsafe { w.duty().bits($start_duty << 4) });
$self.ledc
.int_clr()
.write(|w| { w.[<duty_chng_end_ $speed sch $num _int_clr>]().set_bit() });
.write(|w| { w.[<duty_chng_end_ $speed sch $num>]().clear_bit_by_one() });
}
start_duty_fade!(
$self,
@ -574,7 +574,7 @@ macro_rules! set_duty_fade {
.write(|w| unsafe { w.duty().bits($start_duty << 4) });
$self.ledc
.int_clr()
.write(|w| { w.[<duty_chng_end_ $speed sch $num _int_clr>]().set_bit() });
.write(|w| { w.[<duty_chng_end_ $speed sch $num>]().clear_bit_by_one() });
}
start_duty_fade!(
$self,
@ -598,7 +598,7 @@ macro_rules! set_duty_fade {
.write(|w| unsafe { w.duty().bits($start_duty << 4) });
$self.ledc
.int_clr()
.write(|w| { w.[<duty_chng_end_ch $num _int_clr>]().set_bit() });
.write(|w| { w.[<duty_chng_end_ch $num>]().clear_bit_by_one() });
}
start_duty_fade!(
$self,
@ -620,7 +620,7 @@ macro_rules! is_duty_fade_running {
$self.ledc
.int_raw()
.read()
.[<duty_chng_end_ $speed sch $num _int_raw>]()
.[<duty_chng_end_ $speed sch $num>]()
.bit_is_clear()
}
}};
@ -633,7 +633,7 @@ macro_rules! is_duty_fade_running {
$self.ledc
.int_raw()
.read()
.[<duty_chng_end_ch $num _int_raw>]()
.[<duty_chng_end_ch $num>]()
.bit_is_clear()
}
}};

80
esp-hal/src/parl_io.rs
View File

@ -1064,11 +1064,11 @@ fn internal_listen(interrupts: EnumSet<ParlIoInterrupt>) {
match interrupt {
ParlIoInterrupt::TxFifoReEmpty => parl_io
.int_ena()
.modify(|_, w| w.tx_fifo_rempty_int_ena().set_bit()),
ParlIoInterrupt::RxFifoWOvf => parl_io
.int_ena()
.modify(|_, w| w.rx_fifo_wovf_int_ena().set_bit()),
ParlIoInterrupt::TxEof => parl_io.int_ena().write(|w| w.tx_eof_int_ena().set_bit()),
.modify(|_, w| w.tx_fifo_rempty().set_bit()),
ParlIoInterrupt::RxFifoWOvf => {
parl_io.int_ena().modify(|_, w| w.rx_fifo_wovf().set_bit())
}
ParlIoInterrupt::TxEof => parl_io.int_ena().write(|w| w.tx_eof().set_bit()),
}
}
}
@ -1079,11 +1079,11 @@ fn internal_unlisten(interrupts: EnumSet<ParlIoInterrupt>) {
match interrupt {
ParlIoInterrupt::TxFifoReEmpty => parl_io
.int_ena()
.modify(|_, w| w.tx_fifo_rempty_int_ena().clear_bit()),
.modify(|_, w| w.tx_fifo_rempty().clear_bit()),
ParlIoInterrupt::RxFifoWOvf => parl_io
.int_ena()
.modify(|_, w| w.rx_fifo_wovf_int_ena().clear_bit()),
ParlIoInterrupt::TxEof => parl_io.int_ena().write(|w| w.tx_eof_int_ena().clear_bit()),
.modify(|_, w| w.rx_fifo_wovf().clear_bit()),
ParlIoInterrupt::TxEof => parl_io.int_ena().write(|w| w.tx_eof().clear_bit()),
}
}
}
@ -1092,13 +1092,13 @@ fn internal_interrupts() -> EnumSet<ParlIoInterrupt> {
let mut res = EnumSet::new();
let parl_io = unsafe { crate::peripherals::PARL_IO::steal() };
let ints = parl_io.int_st().read();
if ints.tx_fifo_rempty_int_st().bit() {
if ints.tx_fifo_rempty().bit() {
res.insert(ParlIoInterrupt::TxFifoReEmpty);
}
if ints.rx_fifo_wovf_int_st().bit() {
if ints.rx_fifo_wovf().bit() {
res.insert(ParlIoInterrupt::RxFifoWOvf);
}
if ints.tx_eof_int_st().bit() {
if ints.tx_eof().bit() {
res.insert(ParlIoInterrupt::TxEof);
}
@ -1111,11 +1111,11 @@ fn internal_clear_interrupts(interrupts: EnumSet<ParlIoInterrupt>) {
match interrupt {
ParlIoInterrupt::TxFifoReEmpty => parl_io
.int_clr()
.write(|w| w.tx_fifo_rempty_int_clr().set_bit()),
.write(|w| w.tx_fifo_rempty().clear_bit_by_one()),
ParlIoInterrupt::RxFifoWOvf => parl_io
.int_clr()
.write(|w| w.rx_fifo_wovf_int_clr().set_bit()),
ParlIoInterrupt::TxEof => parl_io.int_clr().write(|w| w.tx_eof_int_clr().set_bit()),
.write(|w| w.rx_fifo_wovf().clear_bit_by_one()),
ParlIoInterrupt::TxEof => parl_io.int_clr().write(|w| w.tx_eof().clear_bit_by_one()),
}
}
}
@ -1838,10 +1838,10 @@ mod private {
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_clr().write(|w| {
w.tx_fifo_rempty_int_clr()
.set_bit()
.tx_eof_int_clr()
.set_bit()
w.tx_fifo_rempty()
.clear_bit_by_one()
.tx_eof()
.clear_bit_by_one()
});
}
@ -1872,7 +1872,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_raw().read().tx_eof_int_raw().bit_is_set()
reg_block.int_raw().read().tx_eof().bit_is_set()
}
pub fn tx_valid_pin_signal() -> crate::gpio::OutputSignal {
@ -1914,7 +1914,7 @@ mod private {
reg_block
.int_clr()
.write(|w| w.rx_fifo_wovf_int_clr().set_bit());
.write(|w| w.rx_fifo_wovf().clear_bit_by_one());
}
pub fn set_rx_bytes(len: u16) {
@ -2018,9 +2018,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block
.int_ena()
.modify(|_, w| w.tx_eof_int_ena().set_bit());
reg_block.int_ena().modify(|_, w| w.tx_eof().set_bit());
}
#[cfg(feature = "async")]
@ -2028,9 +2026,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block
.int_ena()
.modify(|_, w| w.tx_eof_int_ena().clear_bit());
reg_block.int_ena().modify(|_, w| w.tx_eof().clear_bit());
}
#[cfg(feature = "async")]
@ -2038,7 +2034,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_ena().read().tx_eof_int_ena().bit()
reg_block.int_ena().read().tx_eof().bit()
}
#[cfg(feature = "async")]
@ -2046,7 +2042,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_raw().read().tx_eof_int_raw().bit()
reg_block.int_raw().read().tx_eof().bit()
}
#[cfg(feature = "async")]
@ -2054,7 +2050,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_clr().write(|w| w.tx_eof_int_clr().set_bit());
reg_block.int_clr().write(|w| w.tx_eof().clear_bit_by_one());
}
}
@ -2101,10 +2097,10 @@ mod private {
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_clr().write(|w| {
w.tx_fifo_rempty_int_clr()
.set_bit()
.tx_eof_int_clr()
.set_bit()
w.tx_fifo_rempty()
.clear_bit_by_one()
.tx_eof()
.clear_bit_by_one()
});
}
@ -2137,7 +2133,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_raw().read().tx_eof_int_raw().bit_is_set()
reg_block.int_raw().read().tx_eof().bit_is_set()
}
pub fn tx_valid_pin_signal() -> crate::gpio::OutputSignal {
@ -2181,7 +2177,7 @@ mod private {
reg_block
.int_clr()
.write(|w| w.rx_fifo_wovf_int_clr().set_bit());
.write(|w| w.rx_fifo_wovf().clear_bit_by_one());
}
pub fn set_rx_bytes(len: u16) {
@ -2289,9 +2285,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block
.int_ena()
.modify(|_, w| w.tx_eof_int_ena().set_bit());
reg_block.int_ena().modify(|_, w| w.tx_eof().set_bit());
}
#[cfg(feature = "async")]
@ -2299,9 +2293,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block
.int_ena()
.modify(|_, w| w.tx_eof_int_ena().clear_bit());
reg_block.int_ena().modify(|_, w| w.tx_eof().clear_bit());
}
#[cfg(feature = "async")]
@ -2309,7 +2301,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_ena().read().tx_eof_int_ena().bit()
reg_block.int_ena().read().tx_eof().bit()
}
#[cfg(feature = "async")]
@ -2317,7 +2309,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_raw().read().tx_eof_int_raw().bit()
reg_block.int_raw().read().tx_eof().bit()
}
#[cfg(feature = "async")]
@ -2325,7 +2317,7 @@ mod private {
let reg_block: crate::peripherals::PARL_IO =
unsafe { crate::peripherals::PARL_IO::steal() };
reg_block.int_clr().write(|w| w.tx_eof_int_clr().set_bit());
reg_block.int_clr().write(|w| w.tx_eof().clear_bit_by_one());
}
}
}

29
esp-hal/src/rtc_cntl/mod.rs
View File

@ -700,12 +700,7 @@ impl Rwdt {
.wdtconfig0()
.modify(|_, w| unsafe { w.wdt_stg0().bits(self.stg0_action as u8) });
#[cfg(esp32)]
rtc_cntl.int_ena().modify(|_, w| w.wdt_int_ena().set_bit());
#[cfg(not(esp32))]
rtc_cntl
.int_ena_rtc()
.modify(|_, w| w.wdt_int_ena().set_bit());
rtc_cntl.int_ena().modify(|_, w| w.wdt().set_bit());
self.set_write_protection(true);
}
@ -725,14 +720,7 @@ impl Rwdt {
.wdtconfig0()
.modify(|_, w| unsafe { w.wdt_stg0().bits(self.stg0_action as u8) });
#[cfg(esp32)]
rtc_cntl
.int_ena()
.modify(|_, w| w.wdt_int_ena().clear_bit());
#[cfg(not(esp32))]
rtc_cntl
.int_ena_rtc()
.modify(|_, w| w.wdt_int_ena().clear_bit());
rtc_cntl.int_ena().modify(|_, w| w.wdt().clear_bit());
self.set_write_protection(true);
}
@ -745,10 +733,7 @@ impl Rwdt {
self.set_write_protection(false);
#[cfg(esp32)]
rtc_cntl.int_clr().write(|w| w.wdt_int_clr().set_bit());
#[cfg(not(esp32))]
rtc_cntl.int_clr_rtc().write(|w| w.wdt_int_clr().set_bit());
rtc_cntl.int_clr().write(|w| w.wdt().clear_bit_by_one());
self.set_write_protection(true);
}
@ -759,13 +744,7 @@ impl Rwdt {
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
cfg_if::cfg_if! {
if #[cfg(esp32)] {
rtc_cntl.int_st().read().wdt_int_st().bit_is_set()
} else {
rtc_cntl.int_st_rtc().read().wdt_int_st().bit_is_set()
}
}
rtc_cntl.int_st().read().wdt().bit_is_set()
}
pub fn feed(&mut self) {

4
esp-hal/src/rtc_cntl/rtc/esp32c2.rs
View File

@ -47,8 +47,8 @@ pub(crate) fn init() {
power_control_init();
unsafe {
rtc_cntl.int_ena_rtc().write(|w| w.bits(0));
rtc_cntl.int_clr_rtc().write(|w| w.bits(u32::MAX));
rtc_cntl.int_ena().write(|w| w.bits(0));
rtc_cntl.int_clr().write(|w| w.bits(u32::MAX));
}
regi2c_write_mask!(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);

4
esp-hal/src/rtc_cntl/rtc/esp32c3.rs
View File

@ -78,8 +78,8 @@ pub(crate) fn init() {
power_control_init();
unsafe {
rtc_cntl.int_ena_rtc().write(|w| w.bits(0));
rtc_cntl.int_clr_rtc().write(|w| w.bits(u32::MAX));
rtc_cntl.int_ena().write(|w| w.bits(0));
rtc_cntl.int_clr().write(|w| w.bits(u32::MAX));
}
regi2c_write_mask!(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);

12
esp-hal/src/rtc_cntl/sleep/esp32.rs
View File

@ -314,9 +314,7 @@ impl RtcSleepConfig {
.clear_bit()
});
rtc_cntl
.int_ena()
.modify(|_, w| w.brown_out_int_ena().set_bit());
rtc_cntl.int_ena().modify(|_, w| w.brown_out().set_bit());
}
}
@ -550,10 +548,10 @@ impl RtcSleepConfig {
let rtc_cntl = &*esp32::RTC_CNTL::ptr();
rtc_cntl.int_clr().write(|w| {
w.slp_reject_int_clr()
.set_bit()
.slp_wakeup_int_clr()
.set_bit()
w.slp_reject()
.clear_bit_by_one()
.slp_wakeup()
.clear_bit_by_one()
});
// restore DBG_ATTEN to the default value

18
esp-hal/src/rtc_cntl/sleep/esp32c3.rs
View File

@ -102,8 +102,8 @@ impl WakeSource for TimerWakeupSource {
.write(|w| w.slp_val_lo().bits((time_in_ticks & 0xffffffff) as u32));
rtc_cntl
.int_clr_rtc()
.write(|w| w.main_timer_int_clr().set_bit());
.int_clr()
.write(|w| w.main_timer().clear_bit_by_one());
rtc_cntl.slp_timer1().write(|w| {
w.slp_val_hi()
@ -700,8 +700,8 @@ impl RtcSleepConfig {
.dig_pwc()
.modify(|_, w| w.wifi_force_pd().set_bit().bt_force_pd().set_bit());
rtc_cntl.int_ena_rtc().write(|w| w.bits(0));
rtc_cntl.int_clr_rtc().write(|w| w.bits(u32::MAX));
rtc_cntl.int_ena().write(|w| w.bits(0));
rtc_cntl.int_clr().write(|w| w.bits(u32::MAX));
regi2c_write_mask!(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
}
@ -881,11 +881,11 @@ impl RtcSleepConfig {
unsafe {
let rtc_cntl = &*esp32c3::RTC_CNTL::ptr();
rtc_cntl.int_clr_rtc().write(|w| {
w.slp_reject_int_clr()
.set_bit()
.slp_wakeup_int_clr()
.set_bit()
rtc_cntl.int_clr().write(|w| {
w.slp_reject()
.clear_bit_by_one()
.slp_wakeup()
.clear_bit_by_one()
});
// restore config if it is a light sleep

20
esp-hal/src/rtc_cntl/sleep/esp32c6.rs
View File

@ -46,7 +46,7 @@ impl WakeSource for TimerWakeupSource {
});
lp_timer
.int_clr()
.write(|w| w.soc_wakeup_int_clr().set_bit());
.write(|w| w.soc_wakeup().clear_bit_by_one());
lp_timer
.tar0_high()
.modify(|_, w| w.main_timer_tar_en0().set_bit());
@ -951,13 +951,13 @@ impl RtcSleepConfig {
.slp_wakeup_cntl4()
.write(|w| w.slp_reject_cause_clr().bit(true));
pmu().hp_int_clr().write(|w| {
w.sw_int_clr() // pmu_ll_hp_clear_sw_intr_status
.bit(true)
.soc_sleep_reject_int_clr() // pmu_ll_hp_clear_reject_intr_status
.bit(true)
.soc_wakeup_int_clr() // pmu_ll_hp_clear_wakeup_intr_status
.bit(true)
pmu().int_clr().write(|w| {
w.sw() // pmu_ll_hp_clear_sw_intr_status
.clear_bit_by_one()
.soc_sleep_reject() // pmu_ll_hp_clear_reject_intr_status
.clear_bit_by_one()
.soc_wakeup() // pmu_ll_hp_clear_wakeup_intr_status
.clear_bit_by_one()
});
// misc_modules_sleep_prepare
@ -979,9 +979,7 @@ impl RtcSleepConfig {
// In pd_cpu lightsleep and deepsleep mode, we never get here
loop {
let int_raw = pmu().int_raw().read();
if int_raw.soc_wakeup_int_raw().bit_is_set()
|| int_raw.soc_sleep_reject_int_raw().bit_is_set()
{
if int_raw.soc_wakeup().bit_is_set() || int_raw.soc_sleep_reject().bit_is_set() {
break;
}
}

18
esp-hal/src/rtc_cntl/sleep/esp32s3.rs
View File

@ -97,8 +97,8 @@ impl WakeSource for TimerWakeupSource {
.write(|w| w.slp_val_lo().bits((time_in_ticks & 0xffffffff) as u32));
rtc_cntl
.int_clr_rtc()
.write(|w| w.main_timer_int_clr().set_bit());
.int_clr()
.write(|w| w.main_timer().clear_bit_by_one());
rtc_cntl.slp_timer1().write(|w| {
w.slp_val_hi()
@ -690,8 +690,8 @@ impl RtcSleepConfig {
.dig_pwc()
.modify(|_, w| w.wifi_force_pd().set_bit());
rtc_cntl.int_ena_rtc().write(|w| w.bits(0));
rtc_cntl.int_clr_rtc().write(|w| w.bits(u32::MAX));
rtc_cntl.int_ena().write(|w| w.bits(0));
rtc_cntl.int_clr().write(|w| w.bits(u32::MAX));
}
}
@ -896,11 +896,11 @@ impl RtcSleepConfig {
unsafe {
let rtc_cntl = &*esp32s3::RTC_CNTL::ptr();
rtc_cntl.int_clr_rtc().write(|w| {
w.slp_reject_int_clr()
.set_bit()
.slp_wakeup_int_clr()
.set_bit()
rtc_cntl.int_clr().write(|w| {
w.slp_reject()
.clear_bit_by_one()
.slp_wakeup()
.clear_bit_by_one()
});
// restore config if it is a light sleep

14
esp-hal/src/soc/esp32s2/ulp_core.rs
View File

@ -122,13 +122,13 @@ fn ulp_run(wakeup_src: UlpCoreWakeupSource) {
// Clear any spurious wakeup trigger interrupts upon ULP startup
crate::rom::ets_delay_us(20);
rtc_cntl.int_clr_rtc().write(|w| {
w.cocpu_int_clr()
.set_bit()
.cocpu_trap_int_clr()
.set_bit()
.ulp_cp_int_clr()
.set_bit()
rtc_cntl.int_clr().write(|w| {
w.cocpu()
.clear_bit_by_one()
.cocpu_trap()
.clear_bit_by_one()
.ulp_cp()
.clear_bit_by_one()
});
}

14
esp-hal/src/soc/esp32s3/ulp_core.rs
View File

@ -148,13 +148,13 @@ fn ulp_run(wakeup_src: UlpCoreWakeupSource) {
// Clear any spurious wakeup trigger interrupts upon ULP startup
crate::rom::ets_delay_us(20);
rtc_cntl.int_clr_rtc().write(|w| {
w.cocpu_int_clr()
.set_bit()
.cocpu_trap_int_clr()
.set_bit()
.ulp_cp_int_clr()
.set_bit()
rtc_cntl.int_clr().write(|w| {
w.cocpu()
.clear_bit_by_one()
.cocpu_trap()
.clear_bit_by_one()
.ulp_cp()
.clear_bit_by_one()
});
rtc_cntl

68
esp-hal/src/spi/master.rs
View File

@ -1955,16 +1955,16 @@ where
fn clear_dma_interrupts(&self) {
let reg_block = self.register_block();
reg_block.dma_int_clr().write(|w| {
w.dma_infifo_full_err_int_clr()
.set_bit()
.dma_outfifo_empty_err_int_clr()
.set_bit()
.trans_done_int_clr()
.set_bit()
.mst_rx_afifo_wfull_err_int_clr()
.set_bit()
.mst_tx_afifo_rempty_err_int_clr()
.set_bit()
w.dma_infifo_full_err()
.clear_bit_by_one()
.dma_outfifo_empty_err()
.clear_bit_by_one()
.trans_done()
.clear_bit_by_one()
.mst_rx_afifo_wfull_err()
.clear_bit_by_one()
.mst_tx_afifo_rempty_err()
.clear_bit_by_one()
});
}
@ -1972,24 +1972,24 @@ where
fn clear_dma_interrupts(&self) {
let reg_block = self.register_block();
reg_block.dma_int_clr().write(|w| {
w.inlink_dscr_empty_int_clr()
.set_bit()
.outlink_dscr_error_int_clr()
.set_bit()
.inlink_dscr_error_int_clr()
.set_bit()
.in_done_int_clr()
.set_bit()
.in_err_eof_int_clr()
.set_bit()
.in_suc_eof_int_clr()
.set_bit()
.out_done_int_clr()
.set_bit()
.out_eof_int_clr()
.set_bit()
.out_total_eof_int_clr()
.set_bit()
w.inlink_dscr_empty()
.clear_bit_by_one()
.outlink_dscr_error()
.clear_bit_by_one()
.inlink_dscr_error()
.clear_bit_by_one()
.in_done()
.clear_bit_by_one()
.in_err_eof()
.clear_bit_by_one()
.in_suc_eof()
.clear_bit_by_one()
.out_done()
.clear_bit_by_one()
.out_eof()
.clear_bit_by_one()
.out_total_eof()
.clear_bit_by_one()
});
}
}
@ -2405,9 +2405,7 @@ pub trait Instance: crate::private::Sealed {
pre = 16;
}
errval = (apb_clk_freq.raw() as i32 / (pre * n)
- frequency.raw() as i32)
.abs();
errval = (apb_clk_freq.raw() as i32 / (pre * n) - frequency.raw() as i32).abs();
if bestn == -1 || errval <= besterr {
besterr = errval;
bestn = n;
@ -2452,7 +2450,7 @@ pub trait Instance: crate::private::Sealed {
SpiInterrupt::TransDone => {
reg_block
.dma_int_ena()
.modify(|_, w| w.trans_done_int_ena().set_bit());
.modify(|_, w| w.trans_done().set_bit());
}
}
}
@ -2468,7 +2466,7 @@ pub trait Instance: crate::private::Sealed {
SpiInterrupt::TransDone => {
reg_block
.dma_int_ena()
.modify(|_, w| w.trans_done_int_ena().clear_bit());
.modify(|_, w| w.trans_done().clear_bit());
}
}
}
@ -2482,7 +2480,7 @@ pub trait Instance: crate::private::Sealed {
let ints = reg_block.dma_int_st().read();
if ints.trans_done_int_st().bit() {
if ints.trans_done().bit() {
res.insert(SpiInterrupt::TransDone);
}
@ -2499,7 +2497,7 @@ pub trait Instance: crate::private::Sealed {
SpiInterrupt::TransDone => {
reg_block
.dma_int_clr()
.write(|w| w.trans_done_int_clr().set_bit());
.write(|w| w.trans_done().clear_bit_by_one());
}
}
}

64
esp-hal/src/spi/slave.rs
View File

@ -648,16 +648,16 @@ where
fn clear_dma_interrupts(&self) {
let reg_block = self.register_block();
reg_block.dma_int_clr().write(|w| {
w.dma_infifo_full_err_int_clr()
.set_bit()
.dma_outfifo_empty_err_int_clr()
.set_bit()
.trans_done_int_clr()
.set_bit()
.mst_rx_afifo_wfull_err_int_clr()
.set_bit()
.mst_tx_afifo_rempty_err_int_clr()
.set_bit()
w.dma_infifo_full_err()
.clear_bit_by_one()
.dma_outfifo_empty_err()
.clear_bit_by_one()
.trans_done()
.clear_bit_by_one()
.mst_rx_afifo_wfull_err()
.clear_bit_by_one()
.mst_tx_afifo_rempty_err()
.clear_bit_by_one()
});
}
@ -665,24 +665,24 @@ where
fn clear_dma_interrupts(&self) {
let reg_block = self.register_block();
reg_block.dma_int_clr.write(|w| {
w.inlink_dscr_empty_int_clr()
.set_bit()
.outlink_dscr_error_int_clr()
.set_bit()
.inlink_dscr_error_int_clr()
.set_bit()
.in_done_int_clr()
.set_bit()
.in_err_eof_int_clr()
.set_bit()
.in_suc_eof_int_clr()
.set_bit()
.out_done_int_clr()
.set_bit()
.out_eof_int_clr()
.set_bit()
.out_total_eof_int_clr()
.set_bit()
w.inlink_dscr_empty()
.clear_bit_by_one()
.outlink_dscr_error()
.clear_bit_by_one()
.inlink_dscr_error()
.clear_bit_by_one()
.in_done()
.clear_bit_by_one()
.in_err_eof()
.clear_bit_by_one()
.in_suc_eof()
.clear_bit_by_one()
.out_done()
.clear_bit_by_one()
.out_eof()
.clear_bit_by_one()
.out_total_eof()
.clear_bit_by_one()
});
}
}
@ -896,11 +896,7 @@ pub trait Instance: crate::private::Sealed {
}
#[cfg(not(any(esp32, esp32s2)))]
{
reg_block
.dma_int_raw()
.read()
.trans_done_int_raw()
.bit_is_clear()
reg_block.dma_int_raw().read().trans_done().bit_is_clear()
}
}
@ -922,7 +918,7 @@ pub trait Instance: crate::private::Sealed {
#[cfg(not(any(esp32, esp32s2)))]
self.register_block()
.dma_int_clr()
.write(|w| w.trans_done_int_clr().set_bit());
.write(|w| w.trans_done().clear_bit_by_one());
}
}

30
esp-hal/src/systimer.rs
View File

@ -121,15 +121,9 @@ impl<T, const CHANNEL: u8> Alarm<T, CHANNEL> {
pub fn enable_interrupt(&self, val: bool) {
let systimer = unsafe { &*SYSTIMER::ptr() };
match CHANNEL {
0 => systimer
.int_ena()
.modify(|_, w| w.target0_int_ena().bit(val)),
1 => systimer
.int_ena()
.modify(|_, w| w.target1_int_ena().bit(val)),
2 => systimer
.int_ena()
.modify(|_, w| w.target2_int_ena().bit(val)),
0 => systimer.int_ena().modify(|_, w| w.target0().bit(val)),
1 => systimer.int_ena().modify(|_, w| w.target1().bit(val)),
2 => systimer.int_ena().modify(|_, w| w.target2().bit(val)),
_ => unreachable!(),
}
}
@ -137,9 +131,9 @@ impl<T, const CHANNEL: u8> Alarm<T, CHANNEL> {
pub fn clear_interrupt(&self) {
let systimer = unsafe { &*SYSTIMER::ptr() };
match CHANNEL {
0 => systimer.int_clr().write(|w| w.target0_int_clr().set_bit()),
1 => systimer.int_clr().write(|w| w.target1_int_clr().set_bit()),
2 => systimer.int_clr().write(|w| w.target2_int_clr().set_bit()),
0 => systimer.int_clr().write(|w| w.target0().clear_bit_by_one()),
1 => systimer.int_clr().write(|w| w.target1().clear_bit_by_one()),
2 => systimer.int_clr().write(|w| w.target2().clear_bit_by_one()),
_ => unreachable!(),
}
}
@ -335,9 +329,9 @@ mod asynch {
.read();
match N {
0 => r.target0_int_ena().bit_is_clear(),
1 => r.target1_int_ena().bit_is_clear(),
2 => r.target2_int_ena().bit_is_clear(),
0 => r.target0().bit_is_clear(),
1 => r.target1().bit_is_clear(),
2 => r.target2().bit_is_clear(),
_ => unreachable!(),
}
}
@ -376,7 +370,7 @@ mod asynch {
fn SYSTIMER_TARGET0() {
unsafe { &*crate::peripherals::SYSTIMER::PTR }
.int_ena
.modify(|_, w| w.target0_int_ena().clear_bit());
.modify(|_, w| w.target0().clear_bit());
WAKERS[0].wake();
}
@ -385,7 +379,7 @@ mod asynch {
fn SYSTIMER_TARGET1() {
unsafe { &*crate::peripherals::SYSTIMER::PTR }
.int_ena
.modify(|_, w| w.target1_int_ena().clear_bit());
.modify(|_, w| w.target1().clear_bit());
WAKERS[1].wake();
}
@ -394,7 +388,7 @@ mod asynch {
fn SYSTIMER_TARGET2() {
unsafe { &*crate::peripherals::SYSTIMER::PTR }
.int_ena
.modify(|_, w| w.target2_int_ena().clear_bit());
.modify(|_, w| w.target2().clear_bit());
WAKERS[2].wake();
}

24
esp-hal/src/timer.rs
View File

@ -403,17 +403,13 @@ where
.t0config()
.modify(|_, w| w.level_int_en().set_bit());
reg_block
.int_ena_timers()
.modify(|_, w| w.t0_int_ena().set_bit());
reg_block.int_ena_timers().modify(|_, w| w.t0().set_bit());
}
fn unlisten(&mut self) {
let reg_block = unsafe { &*TG::register_block() };
reg_block
.int_ena_timers()
.modify(|_, w| w.t0_int_ena().clear_bit());
reg_block.int_ena_timers().modify(|_, w| w.t0().clear_bit());
}
fn clear_interrupt(&mut self) {
@ -421,7 +417,7 @@ where
reg_block
.int_clr_timers()
.write(|w| w.t0_int_clr().set_bit());
.write(|w| w.t0().clear_bit_by_one());
}
fn now(&self) -> u64 {
@ -455,7 +451,7 @@ where
fn is_interrupt_set(&self) -> bool {
let reg_block = unsafe { &*TG::register_block() };
reg_block.int_raw_timers().read().t0_int_raw().bit_is_set()
reg_block.int_raw_timers().read().t0().bit_is_set()
}
fn set_divider(&mut self, divider: u16) {
@ -577,17 +573,13 @@ where
.t1config()
.modify(|_, w| w.level_int_en().set_bit());
reg_block
.int_ena_timers()
.modify(|_, w| w.t1_int_ena().set_bit());
reg_block.int_ena_timers().modify(|_, w| w.t1().set_bit());
}
fn unlisten(&mut self) {
let reg_block = unsafe { &*TG::register_block() };
reg_block
.int_ena_timers()
.modify(|_, w| w.t1_int_ena().clear_bit());
reg_block.int_ena_timers().modify(|_, w| w.t1().clear_bit());
}
fn clear_interrupt(&mut self) {
@ -595,7 +587,7 @@ where
reg_block
.int_clr_timers()
.write(|w| w.t1_int_clr().set_bit());
.write(|w| w.t1().clear_bit_by_one());
}
fn now(&self) -> u64 {
@ -629,7 +621,7 @@ where
fn is_interrupt_set(&self) -> bool {
let reg_block = unsafe { &*TG::register_block() };
reg_block.int_raw_timers().read().t1_int_raw().bit_is_set()
reg_block.int_raw_timers().read().t1().bit_is_set()
}
fn set_divider(&mut self, divider: u16) {

133
esp-hal/src/uart.rs
View File

@ -711,42 +711,42 @@ where
pub fn listen_at_cmd(&mut self) {
T::register_block()
.int_ena()
.modify(|_, w| w.at_cmd_char_det_int_ena().set_bit());
.modify(|_, w| w.at_cmd_char_det().set_bit());
}
/// Stop listening for AT-CMD interrupts
pub fn unlisten_at_cmd(&mut self) {
T::register_block()
.int_ena()
.modify(|_, w| w.at_cmd_char_det_int_ena().clear_bit());
.modify(|_, w| w.at_cmd_char_det().clear_bit());
}
/// Listen for TX-DONE interrupts
pub fn listen_tx_done(&mut self) {
T::register_block()
.int_ena()
.modify(|_, w| w.tx_done_int_ena().set_bit());
.modify(|_, w| w.tx_done().set_bit());
}
/// Stop listening for TX-DONE interrupts
pub fn unlisten_tx_done(&mut self) {
T::register_block()
.int_ena()
.modify(|_, w| w.tx_done_int_ena().clear_bit());
.modify(|_, w| w.tx_done().clear_bit());
}
/// Listen for RX-FIFO-FULL interrupts
pub fn listen_rx_fifo_full(&mut self) {
T::register_block()
.int_ena()
.modify(|_, w| w.rxfifo_full_int_ena().set_bit());
.modify(|_, w| w.rxfifo_full().set_bit());
}
/// Stop listening for RX-FIFO-FULL interrupts
pub fn unlisten_rx_fifo_full(&mut self) {
T::register_block()
.int_ena()
.modify(|_, w| w.rxfifo_full_int_ena().clear_bit());
.modify(|_, w| w.rxfifo_full().clear_bit());
}
/// Checks if AT-CMD interrupt is set
@ -754,17 +754,13 @@ where
T::register_block()
.int_raw()
.read()
.at_cmd_char_det_int_raw()
.at_cmd_char_det()
.bit_is_set()
}
/// Checks if TX-DONE interrupt is set
pub fn tx_done_interrupt_set(&self) -> bool {
T::register_block()
.int_raw()
.read()
.tx_done_int_raw()
.bit_is_set()
T::register_block().int_raw().read().tx_done().bit_is_set()
}
/// Checks if RX-FIFO-FULL interrupt is set
@ -772,7 +768,7 @@ where
T::register_block()
.int_raw()
.read()
.rxfifo_full_int_raw()
.rxfifo_full()
.bit_is_set()
}
@ -780,21 +776,21 @@ where
pub fn reset_at_cmd_interrupt(&self) {
T::register_block()
.int_clr()
.write(|w| w.at_cmd_char_det_int_clr().set_bit());
.write(|w| w.at_cmd_char_det().clear_bit_by_one());
}
/// Reset TX-DONE interrupt
pub fn reset_tx_done_interrupt(&self) {
T::register_block()
.int_clr()
.write(|w| w.tx_done_int_clr().set_bit());
.write(|w| w.tx_done().clear_bit_by_one());
}
/// Reset RX-FIFO-FULL interrupt
pub fn reset_rx_fifo_full_interrupt(&self) {
T::register_block()
.int_clr()
.write(|w| w.rxfifo_full_int_clr().set_bit());
.write(|w| w.rxfifo_full().clear_bit_by_one());
}
/// Write a byte out over the UART
@ -1096,48 +1092,48 @@ pub trait Instance: crate::private::Sealed {
fn disable_tx_interrupts() {
Self::register_block().int_clr().write(|w| {
w.txfifo_empty_int_clr()
.set_bit()
.tx_brk_done_int_clr()
.set_bit()
.tx_brk_idle_done_int_clr()
.set_bit()
.tx_done_int_clr()
.set_bit()
w.txfifo_empty()
.clear_bit_by_one()
.tx_brk_done()
.clear_bit_by_one()
.tx_brk_idle_done()
.clear_bit_by_one()
.tx_done()
.clear_bit_by_one()
});
Self::register_block().int_ena().write(|w| {
w.txfifo_empty_int_ena()
w.txfifo_empty()
.clear_bit()
.tx_brk_done_int_ena()
.tx_brk_done()
.clear_bit()
.tx_brk_idle_done_int_ena()
.tx_brk_idle_done()
.clear_bit()
.tx_done_int_ena()
.tx_done()
.clear_bit()
});
}
fn disable_rx_interrupts() {
Self::register_block().int_clr().write(|w| {
w.rxfifo_full_int_clr()
.set_bit()
.rxfifo_ovf_int_clr()
.set_bit()
.rxfifo_tout_int_clr()
.set_bit()
.at_cmd_char_det_int_clr()
.set_bit()
w.rxfifo_full()
.clear_bit_by_one()
.rxfifo_ovf()
.clear_bit_by_one()
.rxfifo_tout()
.clear_bit_by_one()
.at_cmd_char_det()
.clear_bit_by_one()
});
Self::register_block().int_ena().write(|w| {
w.rxfifo_full_int_ena()
w.rxfifo_full()
.clear_bit()
.rxfifo_ovf_int_ena()
.rxfifo_ovf()
.clear_bit()
.rxfifo_tout_int_ena()
.rxfifo_tout()
.clear_bit()
.at_cmd_char_det_int_ena()
.at_cmd_char_det()
.clear_bit()
});
}
@ -1615,13 +1611,13 @@ mod asynch {
let mut event_triggered = false;
for event in self.events {
event_triggered |= match event {
RxEvent::RxFifoFull => interrupts_enabled.rxfifo_full_int_ena().bit_is_clear(),
RxEvent::RxFifoFull => interrupts_enabled.rxfifo_full().bit_is_clear(),
RxEvent::RxCmdCharDetected => {
interrupts_enabled.at_cmd_char_det_int_ena().bit_is_clear()
interrupts_enabled.at_cmd_char_det().bit_is_clear()
}
RxEvent::RxFifoOvf => interrupts_enabled.rxfifo_ovf_int_ena().bit_is_clear(),
RxEvent::RxFifoTout => interrupts_enabled.rxfifo_tout_int_ena().bit_is_clear(),
RxEvent::RxFifoOvf => interrupts_enabled.rxfifo_ovf().bit_is_clear(),
RxEvent::RxFifoTout => interrupts_enabled.rxfifo_tout().bit_is_clear(),
}
}
event_triggered
@ -1640,10 +1636,10 @@ mod asynch {
T::register_block().int_ena().modify(|_, w| {
for event in self.events {
match event {
RxEvent::RxFifoFull => w.rxfifo_full_int_ena().set_bit(),
RxEvent::RxCmdCharDetected => w.at_cmd_char_det_int_ena().set_bit(),
RxEvent::RxFifoOvf => w.rxfifo_ovf_int_ena().set_bit(),
RxEvent::RxFifoTout => w.rxfifo_tout_int_ena().set_bit(),
RxEvent::RxFifoFull => w.rxfifo_full().set_bit(),
RxEvent::RxCmdCharDetected => w.at_cmd_char_det().set_bit(),
RxEvent::RxFifoOvf => w.rxfifo_ovf().set_bit(),
RxEvent::RxFifoTout => w.rxfifo_tout().set_bit(),
};
}
w
@ -1666,16 +1662,12 @@ mod asynch {
let int_ena = &T::register_block().int_ena();
for event in self.events {
match event {
RxEvent::RxFifoFull => {
int_ena.modify(|_, w| w.rxfifo_full_int_ena().clear_bit())
}
RxEvent::RxFifoFull => int_ena.modify(|_, w| w.rxfifo_full().clear_bit()),
RxEvent::RxCmdCharDetected => {
int_ena.modify(|_, w| w.at_cmd_char_det_int_ena().clear_bit())
}
RxEvent::RxFifoOvf => int_ena.modify(|_, w| w.rxfifo_ovf_int_ena().clear_bit()),
RxEvent::RxFifoTout => {
int_ena.modify(|_, w| w.rxfifo_tout_int_ena().clear_bit())
int_ena.modify(|_, w| w.at_cmd_char_det().clear_bit())
}
RxEvent::RxFifoOvf => int_ena.modify(|_, w| w.rxfifo_ovf().clear_bit()),
RxEvent::RxFifoTout => int_ena.modify(|_, w| w.rxfifo_tout().clear_bit()),
}
}
}
@ -1695,10 +1687,8 @@ mod asynch {
let mut event_triggered = false;
for event in self.events {
event_triggered |= match event {
TxEvent::TxDone => interrupts_enabled.tx_done_int_ena().bit_is_clear(),
TxEvent::TxFiFoEmpty => {
interrupts_enabled.txfifo_empty_int_ena().bit_is_clear()
}
TxEvent::TxDone => interrupts_enabled.tx_done().bit_is_clear(),
TxEvent::TxFiFoEmpty => interrupts_enabled.txfifo_empty().bit_is_clear(),
}
}
event_triggered
@ -1717,8 +1707,8 @@ mod asynch {
T::register_block().int_ena().modify(|_, w| {
for event in self.events {
match event {
TxEvent::TxDone => w.tx_done_int_ena().set_bit(),
TxEvent::TxFiFoEmpty => w.txfifo_empty_int_ena().set_bit(),
TxEvent::TxDone => w.tx_done().set_bit(),
TxEvent::TxFiFoEmpty => w.txfifo_empty().set_bit(),
};
}
w
@ -1742,10 +1732,8 @@ mod asynch {
let int_ena = &T::register_block().int_ena();
for event in self.events {
match event {
TxEvent::TxDone => int_ena.modify(|_, w| w.tx_done_int_ena().clear_bit()),
TxEvent::TxFiFoEmpty => {
int_ena.modify(|_, w| w.txfifo_empty_int_ena().clear_bit())
}
TxEvent::TxDone => int_ena.modify(|_, w| w.tx_done().clear_bit()),
TxEvent::TxFiFoEmpty => int_ena.modify(|_, w| w.txfifo_empty().clear_bit()),
}
}
}
@ -1900,7 +1888,7 @@ mod asynch {
// reset the counter here, after draining the fifo.
T::register_block()
.int_clr()
.write(|w| w.rxfifo_tout_int_clr().set_bit());
.write(|w| w.rxfifo_tout().clear_bit_by_one());
return Ok(read_bytes);
}
@ -1968,12 +1956,11 @@ mod asynch {
if interrupt_bits == 0 {
return (false, false);
}
let rx_wake = interrupts.rxfifo_full_int_st().bit_is_set()
|| interrupts.rxfifo_ovf_int_st().bit_is_set()
|| interrupts.rxfifo_tout_int_st().bit_is_set()
|| interrupts.at_cmd_char_det_int_st().bit_is_set();
let tx_wake = interrupts.tx_done_int_st().bit_is_set()
|| interrupts.txfifo_empty_int_st().bit_is_set();
let rx_wake = interrupts.rxfifo_full().bit_is_set()
|| interrupts.rxfifo_ovf().bit_is_set()
|| interrupts.rxfifo_tout().bit_is_set()
|| interrupts.at_cmd_char_det().bit_is_set();
let tx_wake = interrupts.tx_done().bit_is_set() || interrupts.txfifo_empty().bit_is_set();
uart.int_clr().write(|w| unsafe { w.bits(interrupt_bits) });
uart.int_ena()
.modify(|r, w| unsafe { w.bits(r.bits() & !interrupt_bits) });

42
esp-hal/src/usb_serial_jtag.rs
View File

@ -172,14 +172,14 @@ impl<'d> UsbSerialJtagRx<'d> {
pub fn listen_rx_packet_recv_interrupt(&mut self) {
USB_DEVICE::register_block()
.int_ena()
.modify(|_, w| w.serial_out_recv_pkt_int_ena().set_bit());
.modify(|_, w| w.serial_out_recv_pkt().set_bit());
}
/// Stop listening for RX-PACKET-RECV interrupts
pub fn unlisten_rx_packet_recv_interrupt(&mut self) {
USB_DEVICE::register_block()
.int_ena()
.modify(|_, w| w.serial_out_recv_pkt_int_ena().clear_bit());
.modify(|_, w| w.serial_out_recv_pkt().clear_bit());
}
/// Checks if RX-PACKET-RECV interrupt is set
@ -187,7 +187,7 @@ impl<'d> UsbSerialJtagRx<'d> {
USB_DEVICE::register_block()
.int_st()
.read()
.serial_out_recv_pkt_int_st()
.serial_out_recv_pkt()
.bit_is_set()
}
@ -195,7 +195,7 @@ impl<'d> UsbSerialJtagRx<'d> {
pub fn reset_rx_packet_recv_interrupt(&mut self) {
USB_DEVICE::register_block()
.int_clr()
.write(|w| w.serial_out_recv_pkt_int_clr().set_bit())
.write(|w| w.serial_out_recv_pkt().clear_bit_by_one())
}
}
@ -291,21 +291,21 @@ pub trait Instance: crate::private::Sealed {
fn disable_tx_interrupts() {
Self::register_block()
.int_ena()
.write(|w| w.serial_in_empty_int_ena().clear_bit());
.write(|w| w.serial_in_empty().clear_bit());
Self::register_block()
.int_clr()
.write(|w| w.serial_in_empty_int_clr().set_bit())
.write(|w| w.serial_in_empty().clear_bit_by_one())
}
fn disable_rx_interrupts() {
Self::register_block()
.int_ena()
.write(|w| w.serial_out_recv_pkt_int_ena().clear_bit());
.write(|w| w.serial_out_recv_pkt().clear_bit());
Self::register_block()
.int_clr()
.write(|w| w.serial_out_recv_pkt_int_clr().set_bit())
.write(|w| w.serial_out_recv_pkt().clear_bit_by_one())
}
}
@ -541,7 +541,7 @@ mod asynch {
// interrupt
USB_DEVICE::register_block()
.int_ena()
.modify(|_, w| w.serial_in_empty_int_ena().set_bit());
.modify(|_, w| w.serial_in_empty().set_bit());
Self {
phantom: PhantomData,
@ -552,7 +552,7 @@ mod asynch {
USB_DEVICE::register_block()
.int_ena()
.read()
.serial_in_empty_int_ena()
.serial_in_empty()
.bit_is_clear()
}
}
@ -583,7 +583,7 @@ mod asynch {
// interrupt
USB_DEVICE::register_block()
.int_ena()
.modify(|_, w| w.serial_out_recv_pkt_int_ena().set_bit());
.modify(|_, w| w.serial_out_recv_pkt().set_bit());
Self {
phantom: PhantomData,
@ -594,7 +594,7 @@ mod asynch {
USB_DEVICE::register_block()
.int_ena()
.read()
.serial_out_recv_pkt_int_ena()
.serial_out_recv_pkt()
.bit_is_clear()
}
}
@ -702,23 +702,21 @@ mod asynch {
let usb = USB_DEVICE::register_block();
let interrupts = usb.int_st().read();
let tx = interrupts.serial_in_empty_int_st().bit_is_set();
let rx = interrupts.serial_out_recv_pkt_int_st().bit_is_set();
let tx = interrupts.serial_in_empty().bit_is_set();
let rx = interrupts.serial_out_recv_pkt().bit_is_set();
if tx {
usb.int_ena()
.write(|w| w.serial_in_empty_int_ena().clear_bit());
usb.int_ena().write(|w| w.serial_in_empty().clear_bit());
}
if rx {
usb.int_ena()
.write(|w| w.serial_out_recv_pkt_int_ena().clear_bit());
usb.int_ena().write(|w| w.serial_out_recv_pkt().clear_bit());
}
usb.int_clr().write(|w| {
w.serial_in_empty_int_clr()
.set_bit()
.serial_out_recv_pkt_int_clr()
.set_bit()
w.serial_in_empty()
.clear_bit_by_one()
.serial_out_recv_pkt()
.clear_bit_by_one()
});
if rx {

6
esp-lp-hal/Cargo.toml
View File

@ -24,9 +24,9 @@ categories = [
cfg-if = "1.0.0"
embedded-hal-02 = { version = "0.2.7", package = "embedded-hal", optional = true, features = ["unproven"] }
embedded-hal-1 = { version = "1.0.0", package = "embedded-hal", optional = true }
esp32c6-lp = { git = "https://github.com/esp-rs/esp-pacs", rev = "ef39b1c", features = ["critical-section"], optional = true }
esp32s2-ulp = { version = "0.1.0", features = ["critical-section"], optional = true }
esp32s3-ulp = { version = "0.1.0", features = ["critical-section"], optional = true }
esp32c6-lp = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32s2-ulp = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32s3-ulp = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
nb = { version = "1.1.0", optional = true }
paste = { version = "1.0.14", optional = true }
procmacros = { package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }

8
esp-lp-hal/src/i2c.rs
View File

@ -457,23 +457,23 @@ impl LpI2c {
fn wait_for_completion(&self) -> Result<(), Error> {
loop {
let interrupts = self.i2c.int_status().read();
let interrupts = self.i2c.int_st().read();
// Handle completion cases
// A full transmission was completed
if interrupts.nack_int_st().bit_is_set() {
if interrupts.nack().bit_is_set() {
self.i2c
.int_clr()
.write(|w| unsafe { w.bits(I2C_LL_INTR_MASK) });
return Err(Error::InvalidResponse);
} else if interrupts.trans_complete_int_st().bit_is_set() {
} else if interrupts.trans_complete().bit_is_set() {
self.disable_interrupts();
self.i2c
.int_clr()
.write(|w| unsafe { w.bits(I2C_LL_INTR_MASK) });
break;
} else if interrupts.end_detect_int_st().bit_is_set() {
} else if interrupts.end_detect().bit_is_set() {
self.i2c
.int_clr()
.write(|w| unsafe { w.bits(I2C_LL_INTR_MASK) });