Re-add API to get a GPIO's interrupt status bit (#929)

* Re-add API to get a GPIO's interrupt status bit

* CHANGELOG.md entry

CHANGELOG.md

@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - ESP32-C6: LP core clock is configurable (#907)
 - Derive `Clone` and `Copy` for `EspTwaiFrame` (#914)
 - A way to configure inverted pins (#912)
+- Added API to check a GPIO-pin's interrupt status bit (#929)
 
 ### Changed
 

esp-hal-common/src/gpio.rs

@@ -186,12 +186,15 @@ pub trait Pin {
 
     fn set_alternate_function(&mut self, alternate: AlternateFunction);
 
+    /// Listen for interrupts
     fn listen(&mut self, event: Event) {
         self.listen_with_options(event, true, false, false)
     }
 
+    /// Checks if listening for interrupts is enabled for this Pin
     fn is_listening(&self) -> bool;
 
+    /// Listen for interrupts
     fn listen_with_options(
         &mut self,
         event: Event,
@@ -200,8 +203,13 @@ pub trait Pin {
         wake_up_from_light_sleep: bool,
     );
 
+    /// Stop listening for interrupts
     fn unlisten(&mut self);
 
+    /// Checks if the interrupt status bit for this Pin is set
+    fn is_interrupt_set(&self) -> bool;
+
+    /// Clear the interrupt status bit for this Pin
     fn clear_interrupt(&mut self);
 }
 
@@ -354,6 +362,8 @@ pub trait BankGpioRegisterAccess {
 
     fn read_output() -> u32;
 
+    fn read_interrupt_status() -> u32;
+
     fn write_interrupt_status_clear(word: u32);
 
     fn write_output_set(word: u32);
@@ -382,6 +392,10 @@ impl BankGpioRegisterAccess for Bank0GpioRegisterAccess {
         unsafe { &*GPIO::PTR }.out.read().bits()
     }
 
+    fn read_interrupt_status() -> u32 {
+        unsafe { &*GPIO::PTR }.status.read().bits()
+    }
+
     fn write_interrupt_status_clear(word: u32) {
         unsafe { &*GPIO::PTR }
             .status_w1tc
@@ -423,6 +437,10 @@ impl BankGpioRegisterAccess for Bank1GpioRegisterAccess {
         unsafe { &*GPIO::PTR }.out1.read().bits()
     }
 
+    fn read_interrupt_status() -> u32 {
+        unsafe { &*GPIO::PTR }.status1.read().bits()
+    }
+
     fn write_interrupt_status_clear(word: u32) {
         unsafe { &*GPIO::PTR }
             .status1_w1tc
@@ -801,6 +819,10 @@ where
         }
     }
 
+    fn is_interrupt_set(&self) -> bool {
+        <Self as GpioProperties>::Bank::read_interrupt_status() & 1 << (GPIONUM % 32) != 0
+    }
+
     fn clear_interrupt(&mut self) {
         <Self as GpioProperties>::Bank::write_interrupt_status_clear(1 << (GPIONUM % 32));
     }