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Remove Dma[Rx|Tx]Buffer::length (#2587)

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Co-authored-by: Dominic Fischer <git@dominicfischer.me>
This commit is contained in:
Dominic Fischer 2024-12-03 08:27:13 +00:00 committed by GitHub
parent a6a83d3bb5
commit 94e7ffbcef
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GPG Key ID: B5690EEEBB952194
11 changed files with 184 additions and 95 deletions
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2
esp-hal/CHANGELOG.md
View File

@ -39,6 +39,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- `SystemTimer` no longer uses peripheral ref (#2576)
- `TIMGX` no longer uses peripheral ref (#2581)
- `SystemTimer::now` has been renamed `SystemTimer::unit_value(Unit)` (#2576)
- `SpiDma` transfers now explicitly take a length along with the DMA buffer object (#2587)
- `dma::{Channel, ChannelRx, ChannelTx}::set_priority` for GDMA devices (#2403)
- `SystemTimer`s `Alarm`s are now type erased (#2576)
- `TimerGroup` `Timer`s are now type erased (#2581)
@ -66,6 +67,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- The DMA channel objects no longer have `tx` and `rx` fields. (#2526)
- `SysTimerAlarms` has been removed, alarms are now part of the `SystemTimer` struct (#2576)
- `FrozenUnit`, `AnyUnit`, `SpecificUnit`, `SpecificComparator`, `AnyComparator` have been removed from `systimer` (#2576)
- Remove Dma[Rx|Tx]Buffer::length (#2587)
- `esp_hal::psram::psram_range` (#2546)
- The `Dma` structure has been removed. (#2545)
- Removed `embedded-hal 0.2.x` impls and deps from `esp-hal` (#2593)

21
esp-hal/MIGRATING-0.22.md
View File

@ -273,3 +273,24 @@ is not compatible with the hardware.
+ cam_config,
)
```
## SpiDma now requires you specify the transfer length explicitly
```diff
dma_tx_buf.set_length(5 /* or greater */);
- spi_dma.write(dma_tx_buf);
+ spi_dma.write(5, dma_tx_buf);
```
```diff
dma_rx_buf.set_length(5 /* or greater */);
- spi_dma.read(dma_rx_buf);
+ spi_dma.read(5, dma_rx_buf);
```
```diff
dma_rx_buf.set_length(5 /* or greater */);
dma_tx_buf.set_length(5 /* or greater */);
- spi_dma.transfer(dma_rx_buf, dma_tx_buf);
+ spi_dma.transfer(5, dma_rx_buf, 5, dma_tx_buf);
```

45
esp-hal/src/dma/buffers.rs
View File

@ -120,13 +120,6 @@ pub unsafe trait DmaTxBuffer {
/// This is called after the DMA is done using the buffer.
fn from_view(view: Self::View) -> Self;
/// Returns the maximum number of bytes that would be transmitted by this
/// buffer.
///
/// This is a convenience hint for SPI. Most peripherals don't care how long
/// the transfer is.
fn length(&self) -> usize;
}
/// [DmaRxBuffer] is a DMA descriptor + memory combo that can be used for
@ -156,12 +149,6 @@ pub unsafe trait DmaRxBuffer {
/// This is called after the DMA is done using the buffer.
fn from_view(view: Self::View) -> Self;
/// Returns the maximum number of bytes that can be received by this buffer.
///
/// This is a convenience hint for SPI. Most peripherals don't care how long
/// the transfer is.
fn length(&self) -> usize;
}
/// An in-progress view into [DmaRxBuf]/[DmaTxBuf].
@ -387,10 +374,6 @@ unsafe impl DmaTxBuffer for DmaTxBuf {
fn from_view(view: Self::View) -> Self {
view.0
}
fn length(&self) -> usize {
self.len()
}
}
/// DMA receive buffer
@ -543,10 +526,6 @@ unsafe impl DmaRxBuffer for DmaRxBuf {
fn from_view(view: Self::View) -> Self {
view.0
}
fn length(&self) -> usize {
self.len()
}
}
/// DMA transmit and receive buffer.
@ -675,10 +654,6 @@ unsafe impl DmaTxBuffer for DmaRxTxBuf {
fn from_view(view: Self::View) -> Self {
view.0
}
fn length(&self) -> usize {
self.len()
}
}
unsafe impl DmaRxBuffer for DmaRxTxBuf {
@ -711,10 +686,6 @@ unsafe impl DmaRxBuffer for DmaRxTxBuf {
fn from_view(view: Self::View) -> Self {
view.0
}
fn length(&self) -> usize {
self.len()
}
}
/// DMA Streaming Receive Buffer.
@ -865,10 +836,6 @@ unsafe impl DmaRxBuffer for DmaRxStreamBuf {
fn from_view(view: Self::View) -> Self {
view.buf
}
fn length(&self) -> usize {
panic!("DmaCircularBuf doesn't have a length")
}
}
/// A view into a [DmaRxStreamBuf]
@ -1072,10 +1039,6 @@ unsafe impl DmaTxBuffer for EmptyBuf {
fn from_view(view: Self::View) -> Self {
view
}
fn length(&self) -> usize {
0
}
}
unsafe impl DmaRxBuffer for EmptyBuf {
@ -1103,10 +1066,6 @@ unsafe impl DmaRxBuffer for EmptyBuf {
fn from_view(view: Self::View) -> Self {
view
}
fn length(&self) -> usize {
0
}
}
/// DMA Loop Buffer
@ -1180,10 +1139,6 @@ unsafe impl DmaTxBuffer for DmaLoopBuf {
fn from_view(view: Self::View) -> Self {
view
}
fn length(&self) -> usize {
panic!("DmaLoopBuf does not have a length")
}
}
impl Deref for DmaLoopBuf {

137
esp-hal/src/spi/master.rs
View File

@ -1063,12 +1063,11 @@ mod dma {
unsafe fn start_transfer_dma<RX: DmaRxBuffer, TX: DmaTxBuffer>(
&mut self,
full_duplex: bool,
bytes_to_read: usize,
bytes_to_write: usize,
rx_buffer: &mut RX,
tx_buffer: &mut TX,
) -> Result<(), Error> {
let bytes_to_read = rx_buffer.length();
let bytes_to_write = tx_buffer.length();
if bytes_to_read > MAX_DMA_SIZE || bytes_to_write > MAX_DMA_SIZE {
return Err(Error::MaxDmaTransferSizeExceeded);
}
@ -1078,6 +1077,8 @@ mod dma {
unsafe {
self.dma_driver().start_transfer_dma(
full_duplex,
bytes_to_read,
bytes_to_write,
rx_buffer,
tx_buffer,
&mut self.channel.rx,
@ -1116,6 +1117,8 @@ mod dma {
unsafe {
self.dma_driver().start_transfer_dma(
false,
0,
bytes_to_write,
&mut EmptyBuf,
&mut self.address_buffer,
&mut self.channel.rx,
@ -1275,8 +1278,12 @@ mod dma {
/// The caller must ensure that the buffers are not accessed while the
/// transfer is in progress. Moving the buffers is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
unsafe fn start_dma_write(&mut self, buffer: &mut impl DmaTxBuffer) -> Result<(), Error> {
self.start_dma_transfer(&mut EmptyBuf, buffer)
unsafe fn start_dma_write(
&mut self,
bytes_to_write: usize,
buffer: &mut impl DmaTxBuffer,
) -> Result<(), Error> {
self.start_dma_transfer(0, bytes_to_write, &mut EmptyBuf, buffer)
}
/// Perform a DMA write.
@ -1288,11 +1295,12 @@ mod dma {
#[cfg_attr(place_spi_driver_in_ram, ram)]
pub fn write<TX: DmaTxBuffer>(
mut self,
bytes_to_write: usize,
mut buffer: TX,
) -> Result<SpiDmaTransfer<'d, M, TX, T>, (Error, Self, TX)> {
self.wait_for_idle();
match unsafe { self.start_dma_write(&mut buffer) } {
match unsafe { self.start_dma_write(bytes_to_write, &mut buffer) } {
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
Err(e) => Err((e, self, buffer)),
}
@ -1303,8 +1311,12 @@ mod dma {
/// The caller must ensure that the buffers are not accessed while the
/// transfer is in progress. Moving the buffers is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
unsafe fn start_dma_read(&mut self, buffer: &mut impl DmaRxBuffer) -> Result<(), Error> {
self.start_dma_transfer(buffer, &mut EmptyBuf)
unsafe fn start_dma_read(
&mut self,
bytes_to_read: usize,
buffer: &mut impl DmaRxBuffer,
) -> Result<(), Error> {
self.start_dma_transfer(bytes_to_read, 0, buffer, &mut EmptyBuf)
}
/// Perform a DMA read.
@ -1316,10 +1328,11 @@ mod dma {
#[cfg_attr(place_spi_driver_in_ram, ram)]
pub fn read<RX: DmaRxBuffer>(
mut self,
bytes_to_read: usize,
mut buffer: RX,
) -> Result<SpiDmaTransfer<'d, M, RX, T>, (Error, Self, RX)> {
self.wait_for_idle();
match unsafe { self.start_dma_read(&mut buffer) } {
match unsafe { self.start_dma_read(bytes_to_read, &mut buffer) } {
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
Err(e) => Err((e, self, buffer)),
}
@ -1332,10 +1345,12 @@ mod dma {
#[cfg_attr(place_spi_driver_in_ram, ram)]
unsafe fn start_dma_transfer(
&mut self,
bytes_to_read: usize,
bytes_to_write: usize,
rx_buffer: &mut impl DmaRxBuffer,
tx_buffer: &mut impl DmaTxBuffer,
) -> Result<(), Error> {
self.start_transfer_dma(true, rx_buffer, tx_buffer)
self.start_transfer_dma(true, bytes_to_read, bytes_to_write, rx_buffer, tx_buffer)
}
/// Perform a DMA transfer
@ -1347,11 +1362,20 @@ mod dma {
#[cfg_attr(place_spi_driver_in_ram, ram)]
pub fn transfer<RX: DmaRxBuffer, TX: DmaTxBuffer>(
mut self,
bytes_to_read: usize,
mut rx_buffer: RX,
bytes_to_write: usize,
mut tx_buffer: TX,
) -> Result<SpiDmaTransfer<'d, M, (RX, TX), T>, (Error, Self, RX, TX)> {
self.wait_for_idle();
match unsafe { self.start_dma_transfer(&mut rx_buffer, &mut tx_buffer) } {
match unsafe {
self.start_dma_transfer(
bytes_to_read,
bytes_to_write,
&mut rx_buffer,
&mut tx_buffer,
)
} {
Ok(_) => Ok(SpiDmaTransfer::new(self, (rx_buffer, tx_buffer))),
Err(e) => Err((e, self, rx_buffer, tx_buffer)),
}
@ -1368,10 +1392,9 @@ mod dma {
cmd: Command,
address: Address,
dummy: u8,
bytes_to_read: usize,
buffer: &mut impl DmaRxBuffer,
) -> Result<(), Error> {
let bytes_to_read = buffer.length();
self.driver().setup_half_duplex(
false,
cmd,
@ -1382,7 +1405,7 @@ mod dma {
data_mode,
);
self.start_transfer_dma(false, buffer, &mut EmptyBuf)
self.start_transfer_dma(false, bytes_to_read, 0, buffer, &mut EmptyBuf)
}
/// Perform a half-duplex read operation using DMA.
@ -1394,12 +1417,20 @@ mod dma {
cmd: Command,
address: Address,
dummy: u8,
bytes_to_read: usize,
mut buffer: RX,
) -> Result<SpiDmaTransfer<'d, M, RX, T>, (Error, Self, RX)> {
self.wait_for_idle();
match unsafe {
self.start_half_duplex_read(data_mode, cmd, address, dummy, &mut buffer)
self.start_half_duplex_read(
data_mode,
cmd,
address,
dummy,
bytes_to_read,
&mut buffer,
)
} {
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
Err(e) => Err((e, self, buffer)),
@ -1417,10 +1448,9 @@ mod dma {
cmd: Command,
address: Address,
dummy: u8,
bytes_to_write: usize,
buffer: &mut impl DmaTxBuffer,
) -> Result<(), Error> {
let bytes_to_write = buffer.length();
#[cfg(all(esp32, spi_address_workaround))]
{
// On the ESP32, if we don't have data, the address is always sent
@ -1440,7 +1470,7 @@ mod dma {
data_mode,
);
self.start_transfer_dma(false, &mut EmptyBuf, buffer)
self.start_transfer_dma(false, 0, bytes_to_write, &mut EmptyBuf, buffer)
}
/// Perform a half-duplex write operation using DMA.
@ -1452,12 +1482,20 @@ mod dma {
cmd: Command,
address: Address,
dummy: u8,
bytes_to_write: usize,
mut buffer: TX,
) -> Result<SpiDmaTransfer<'d, M, TX, T>, (Error, Self, TX)> {
self.wait_for_idle();
match unsafe {
self.start_half_duplex_write(data_mode, cmd, address, dummy, &mut buffer)
self.start_half_duplex_write(
data_mode,
cmd,
address,
dummy,
bytes_to_write,
&mut buffer,
)
} {
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
Err(e) => Err((e, self, buffer)),
@ -1590,8 +1628,12 @@ mod dma {
self.rx_buf.set_length(chunk.len());
unsafe {
self.spi_dma
.start_dma_transfer(&mut self.rx_buf, &mut EmptyBuf)?;
self.spi_dma.start_dma_transfer(
chunk.len(),
0,
&mut self.rx_buf,
&mut EmptyBuf,
)?;
}
self.wait_for_idle();
@ -1610,8 +1652,12 @@ mod dma {
self.tx_buf.fill(chunk);
unsafe {
self.spi_dma
.start_dma_transfer(&mut EmptyBuf, &mut self.tx_buf)?;
self.spi_dma.start_dma_transfer(
chunk.len(),
0,
&mut EmptyBuf,
&mut self.tx_buf,
)?;
}
self.wait_for_idle();
@ -1637,8 +1683,12 @@ mod dma {
self.rx_buf.set_length(read_chunk.len());
unsafe {
self.spi_dma
.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
self.spi_dma.start_dma_transfer(
read_chunk.len(),
write_chunk.len(),
&mut self.rx_buf,
&mut self.tx_buf,
)?;
}
self.wait_for_idle();
@ -1665,8 +1715,12 @@ mod dma {
self.rx_buf.set_length(chunk.len());
unsafe {
self.spi_dma
.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
self.spi_dma.start_dma_transfer(
chunk.len(),
chunk.len(),
&mut self.rx_buf,
&mut self.tx_buf,
)?;
}
self.wait_for_idle();
@ -1698,6 +1752,7 @@ mod dma {
cmd,
address,
dummy,
buffer.len(),
&mut self.rx_buf,
)?;
}
@ -1731,6 +1786,7 @@ mod dma {
cmd,
address,
dummy,
buffer.len(),
&mut self.tx_buf,
)?;
}
@ -1816,7 +1872,9 @@ mod dma {
let mut spi = DropGuard::new(&mut self.spi_dma, |spi| spi.cancel_transfer());
unsafe { spi.start_dma_transfer(&mut self.rx_buf, &mut EmptyBuf)? };
unsafe {
spi.start_dma_transfer(chunk.len(), 0, &mut self.rx_buf, &mut EmptyBuf)?
};
spi.wait_for_idle_async().await;
@ -1839,7 +1897,9 @@ mod dma {
for chunk in words.chunks(chunk_size) {
self.tx_buf.fill(chunk);
unsafe { spi.start_dma_transfer(&mut EmptyBuf, &mut self.tx_buf)? };
unsafe {
spi.start_dma_transfer(0, chunk.len(), &mut EmptyBuf, &mut self.tx_buf)?
};
spi.wait_for_idle_async().await;
}
@ -1872,7 +1932,12 @@ mod dma {
self.rx_buf.set_length(read_chunk.len());
unsafe {
spi.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
spi.start_dma_transfer(
read_chunk.len(),
write_chunk.len(),
&mut self.rx_buf,
&mut self.tx_buf,
)?;
}
spi.wait_for_idle_async().await;
@ -1902,7 +1967,12 @@ mod dma {
self.rx_buf.set_length(chunk.len());
unsafe {
spi.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
spi.start_dma_transfer(
chunk.len(),
chunk.len(),
&mut self.rx_buf,
&mut self.tx_buf,
)?;
}
spi.wait_for_idle_async().await;
@ -2147,10 +2217,13 @@ impl DmaDriver {
self.info.update();
}
#[allow(clippy::too_many_arguments)]
#[cfg_attr(place_spi_driver_in_ram, ram)]
unsafe fn start_transfer_dma<RX: Rx, TX: Tx>(
&self,
_full_duplex: bool,
rx_len: usize,
tx_len: usize,
rx_buffer: &mut impl DmaRxBuffer,
tx_buffer: &mut impl DmaTxBuffer,
rx: &mut RX,
@ -2165,8 +2238,6 @@ impl DmaDriver {
reg_block.dma_in_link().write(|w| w.bits(0));
}
let rx_len = rx_buffer.length();
let tx_len = tx_buffer.length();
self.info.configure_datalen(rx_len, tx_len);
// enable the MISO and MOSI if needed

2
examples/src/bin/spi_loopback_dma_psram.rs
View File

@ -115,7 +115,7 @@ fn main() -> ! {
i = i.wrapping_add(1);
let transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();

10
hil-test/tests/qspi.rs
View File

@ -53,7 +53,14 @@ fn transfer_read(
command: Command,
) -> (SpiUnderTest, DmaRxBuf) {
let transfer = spi
.half_duplex_read(SpiDataMode::Quad, command, Address::None, 0, dma_rx_buf)
.half_duplex_read(
SpiDataMode::Quad,
command,
Address::None,
0,
dma_rx_buf.len(),
dma_rx_buf,
)
.map_err(|e| e.0)
.unwrap();
transfer.wait()
@ -74,6 +81,7 @@ fn transfer_write(
SpiDataMode::Quad,
),
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)

51
hil-test/tests/spi_full_duplex.rs
View File

@ -208,11 +208,17 @@ mod tests {
for i in 1..4 {
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
let transfer = spi
.read(dma_rx_buf.len(), dma_rx_buf)
.map_err(|e| e.0)
.unwrap();
(spi, dma_rx_buf) = transfer.wait();
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
let transfer = spi
.write(dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
(spi, dma_tx_buf) = transfer.wait();
assert_eq!(unit.value(), (i * 3 * DMA_BUFFER_SIZE) as _);
}
@ -239,12 +245,15 @@ mod tests {
for i in 1..4 {
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
let transfer = spi
.read(dma_rx_buf.len(), dma_rx_buf)
.map_err(|e| e.0)
.unwrap();
(spi, dma_rx_buf) = transfer.wait();
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
let transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
@ -269,7 +278,7 @@ mod tests {
dma_tx_buf.as_mut_slice()[0] = i as u8;
*dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
let transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
@ -293,7 +302,7 @@ mod tests {
let spi = ctx.spi.with_dma(ctx.dma_channel);
let transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
let (spi, (dma_rx_buf, mut dma_tx_buf)) = transfer.wait();
@ -304,7 +313,7 @@ mod tests {
dma_tx_buf.fill(&[0xaa, 0xdd, 0xef, 0xbe]);
let transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
@ -458,18 +467,30 @@ mod tests {
dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
let transfer = spi
.write(dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
let (spi, dma_tx_buf) = transfer.wait();
dma_rx_buf.as_mut_slice().fill(0);
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
let transfer = spi
.read(dma_rx_buf.len(), dma_rx_buf)
.map_err(|e| e.0)
.unwrap();
let (spi, mut dma_rx_buf) = transfer.wait();
let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
let transfer = spi
.write(dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
let (spi, _dma_tx_buf) = transfer.wait();
dma_rx_buf.as_mut_slice().fill(0);
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
let transfer = spi
.read(dma_rx_buf.len(), dma_rx_buf)
.map_err(|e| e.0)
.unwrap();
let (_, dma_rx_buf) = transfer.wait();
assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
@ -492,7 +513,7 @@ mod tests {
let spi = ctx.spi.with_dma(ctx.dma_channel);
let mut transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
@ -515,7 +536,7 @@ mod tests {
let mut spi = ctx.spi.with_dma(ctx.dma_channel);
let mut transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
@ -526,7 +547,7 @@ mod tests {
.unwrap();
let transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();
@ -548,7 +569,7 @@ mod tests {
let spi = ctx.spi.with_dma(ctx.dma_channel).into_async();
let mut transfer = spi
.transfer(dma_rx_buf, dma_tx_buf)
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
.map_err(|e| e.0)
.unwrap();

2
hil-test/tests/spi_half_duplex_read.rs
View File

@ -79,6 +79,7 @@ mod tests {
Command::None,
Address::None,
0,
dma_rx_buf.len(),
dma_rx_buf,
)
.map_err(|e| e.0)
@ -96,6 +97,7 @@ mod tests {
Command::None,
Address::None,
0,
dma_rx_buf.len(),
dma_rx_buf,
)
.map_err(|e| e.0)

2
hil-test/tests/spi_half_duplex_write.rs
View File

@ -92,6 +92,7 @@ mod tests {
Command::None,
Address::None,
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)
@ -106,6 +107,7 @@ mod tests {
Command::None,
Address::None,
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)

2
hil-test/tests/spi_half_duplex_write_psram.rs
View File

@ -107,6 +107,7 @@ mod tests {
Command::None,
Address::None,
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)
@ -121,6 +122,7 @@ mod tests {
Command::None,
Address::None,
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)

5
qa-test/src/bin/qspi_flash.rs
View File

@ -100,6 +100,7 @@ fn main() -> ! {
Command::Command8(0x06, SpiDataMode::Single),
Address::None,
0,
0,
dma_tx_buf,
)
.map_err(|e| e.0)
@ -114,6 +115,7 @@ fn main() -> ! {
Command::Command8(0x20, SpiDataMode::Single),
Address::Address24(0x000000, SpiDataMode::Single),
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)
@ -128,6 +130,7 @@ fn main() -> ! {
Command::Command8(0x06, SpiDataMode::Single),
Address::None,
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)
@ -145,6 +148,7 @@ fn main() -> ! {
Command::Command8(0x32, SpiDataMode::Single),
Address::Address24(0x000000, SpiDataMode::Single),
0,
dma_tx_buf.len(),
dma_tx_buf,
)
.map_err(|e| e.0)
@ -160,6 +164,7 @@ fn main() -> ! {
Command::Command8(0xeb, SpiDataMode::Single),
Address::Address32(0x000000 << 8, SpiDataMode::Quad),
4,
dma_rx_buf.len(),
dma_rx_buf,
)
.map_err(|e| e.0)