Remove Dma[Rx|Tx]Buffer::length (#2587)
Co-authored-by: Dominic Fischer <git@dominicfischer.me>
This commit is contained in:
parent
a6a83d3bb5
commit
94e7ffbcef
@ -39,6 +39,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- `SystemTimer` no longer uses peripheral ref (#2576)
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- `SystemTimer` no longer uses peripheral ref (#2576)
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- `TIMGX` no longer uses peripheral ref (#2581)
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- `TIMGX` no longer uses peripheral ref (#2581)
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- `SystemTimer::now` has been renamed `SystemTimer::unit_value(Unit)` (#2576)
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- `SystemTimer::now` has been renamed `SystemTimer::unit_value(Unit)` (#2576)
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- `SpiDma` transfers now explicitly take a length along with the DMA buffer object (#2587)
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- `dma::{Channel, ChannelRx, ChannelTx}::set_priority` for GDMA devices (#2403)
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- `dma::{Channel, ChannelRx, ChannelTx}::set_priority` for GDMA devices (#2403)
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- `SystemTimer`s `Alarm`s are now type erased (#2576)
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- `SystemTimer`s `Alarm`s are now type erased (#2576)
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- `TimerGroup` `Timer`s are now type erased (#2581)
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- `TimerGroup` `Timer`s are now type erased (#2581)
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@ -66,6 +67,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- The DMA channel objects no longer have `tx` and `rx` fields. (#2526)
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- The DMA channel objects no longer have `tx` and `rx` fields. (#2526)
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- `SysTimerAlarms` has been removed, alarms are now part of the `SystemTimer` struct (#2576)
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- `SysTimerAlarms` has been removed, alarms are now part of the `SystemTimer` struct (#2576)
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- `FrozenUnit`, `AnyUnit`, `SpecificUnit`, `SpecificComparator`, `AnyComparator` have been removed from `systimer` (#2576)
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- `FrozenUnit`, `AnyUnit`, `SpecificUnit`, `SpecificComparator`, `AnyComparator` have been removed from `systimer` (#2576)
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- Remove Dma[Rx|Tx]Buffer::length (#2587)
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- `esp_hal::psram::psram_range` (#2546)
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- `esp_hal::psram::psram_range` (#2546)
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- The `Dma` structure has been removed. (#2545)
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- The `Dma` structure has been removed. (#2545)
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- Removed `embedded-hal 0.2.x` impls and deps from `esp-hal` (#2593)
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- Removed `embedded-hal 0.2.x` impls and deps from `esp-hal` (#2593)
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@ -273,3 +273,24 @@ is not compatible with the hardware.
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+ cam_config,
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+ cam_config,
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)
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)
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```
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```
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## SpiDma now requires you specify the transfer length explicitly
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```diff
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dma_tx_buf.set_length(5 /* or greater */);
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- spi_dma.write(dma_tx_buf);
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+ spi_dma.write(5, dma_tx_buf);
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```
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```diff
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dma_rx_buf.set_length(5 /* or greater */);
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- spi_dma.read(dma_rx_buf);
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+ spi_dma.read(5, dma_rx_buf);
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```
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```diff
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dma_rx_buf.set_length(5 /* or greater */);
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dma_tx_buf.set_length(5 /* or greater */);
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- spi_dma.transfer(dma_rx_buf, dma_tx_buf);
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+ spi_dma.transfer(5, dma_rx_buf, 5, dma_tx_buf);
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```
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@ -120,13 +120,6 @@ pub unsafe trait DmaTxBuffer {
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/// This is called after the DMA is done using the buffer.
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/// This is called after the DMA is done using the buffer.
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fn from_view(view: Self::View) -> Self;
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fn from_view(view: Self::View) -> Self;
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/// Returns the maximum number of bytes that would be transmitted by this
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/// buffer.
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///
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/// This is a convenience hint for SPI. Most peripherals don't care how long
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/// the transfer is.
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fn length(&self) -> usize;
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}
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}
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/// [DmaRxBuffer] is a DMA descriptor + memory combo that can be used for
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/// [DmaRxBuffer] is a DMA descriptor + memory combo that can be used for
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@ -156,12 +149,6 @@ pub unsafe trait DmaRxBuffer {
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/// This is called after the DMA is done using the buffer.
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/// This is called after the DMA is done using the buffer.
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fn from_view(view: Self::View) -> Self;
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fn from_view(view: Self::View) -> Self;
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/// Returns the maximum number of bytes that can be received by this buffer.
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///
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/// This is a convenience hint for SPI. Most peripherals don't care how long
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/// the transfer is.
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fn length(&self) -> usize;
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}
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}
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/// An in-progress view into [DmaRxBuf]/[DmaTxBuf].
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/// An in-progress view into [DmaRxBuf]/[DmaTxBuf].
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@ -387,10 +374,6 @@ unsafe impl DmaTxBuffer for DmaTxBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view.0
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view.0
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}
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}
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fn length(&self) -> usize {
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self.len()
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}
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}
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}
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/// DMA receive buffer
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/// DMA receive buffer
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@ -543,10 +526,6 @@ unsafe impl DmaRxBuffer for DmaRxBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view.0
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view.0
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}
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}
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fn length(&self) -> usize {
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self.len()
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}
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}
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}
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/// DMA transmit and receive buffer.
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/// DMA transmit and receive buffer.
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@ -675,10 +654,6 @@ unsafe impl DmaTxBuffer for DmaRxTxBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view.0
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view.0
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}
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}
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fn length(&self) -> usize {
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self.len()
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}
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}
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}
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unsafe impl DmaRxBuffer for DmaRxTxBuf {
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unsafe impl DmaRxBuffer for DmaRxTxBuf {
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@ -711,10 +686,6 @@ unsafe impl DmaRxBuffer for DmaRxTxBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view.0
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view.0
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}
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}
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fn length(&self) -> usize {
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self.len()
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}
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}
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}
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/// DMA Streaming Receive Buffer.
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/// DMA Streaming Receive Buffer.
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@ -865,10 +836,6 @@ unsafe impl DmaRxBuffer for DmaRxStreamBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view.buf
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view.buf
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}
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}
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fn length(&self) -> usize {
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panic!("DmaCircularBuf doesn't have a length")
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}
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}
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}
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/// A view into a [DmaRxStreamBuf]
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/// A view into a [DmaRxStreamBuf]
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@ -1072,10 +1039,6 @@ unsafe impl DmaTxBuffer for EmptyBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view
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view
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}
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}
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fn length(&self) -> usize {
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0
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}
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}
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}
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unsafe impl DmaRxBuffer for EmptyBuf {
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unsafe impl DmaRxBuffer for EmptyBuf {
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@ -1103,10 +1066,6 @@ unsafe impl DmaRxBuffer for EmptyBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view
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view
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}
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}
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fn length(&self) -> usize {
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0
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}
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}
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}
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/// DMA Loop Buffer
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/// DMA Loop Buffer
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@ -1180,10 +1139,6 @@ unsafe impl DmaTxBuffer for DmaLoopBuf {
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fn from_view(view: Self::View) -> Self {
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fn from_view(view: Self::View) -> Self {
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view
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view
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}
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}
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fn length(&self) -> usize {
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panic!("DmaLoopBuf does not have a length")
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}
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}
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}
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impl Deref for DmaLoopBuf {
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impl Deref for DmaLoopBuf {
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@ -1063,12 +1063,11 @@ mod dma {
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unsafe fn start_transfer_dma<RX: DmaRxBuffer, TX: DmaTxBuffer>(
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unsafe fn start_transfer_dma<RX: DmaRxBuffer, TX: DmaTxBuffer>(
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&mut self,
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&mut self,
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full_duplex: bool,
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full_duplex: bool,
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bytes_to_read: usize,
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bytes_to_write: usize,
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rx_buffer: &mut RX,
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rx_buffer: &mut RX,
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tx_buffer: &mut TX,
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tx_buffer: &mut TX,
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) -> Result<(), Error> {
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) -> Result<(), Error> {
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let bytes_to_read = rx_buffer.length();
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let bytes_to_write = tx_buffer.length();
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if bytes_to_read > MAX_DMA_SIZE || bytes_to_write > MAX_DMA_SIZE {
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if bytes_to_read > MAX_DMA_SIZE || bytes_to_write > MAX_DMA_SIZE {
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return Err(Error::MaxDmaTransferSizeExceeded);
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return Err(Error::MaxDmaTransferSizeExceeded);
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}
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}
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@ -1078,6 +1077,8 @@ mod dma {
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unsafe {
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unsafe {
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self.dma_driver().start_transfer_dma(
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self.dma_driver().start_transfer_dma(
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full_duplex,
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full_duplex,
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bytes_to_read,
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bytes_to_write,
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rx_buffer,
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rx_buffer,
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tx_buffer,
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tx_buffer,
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&mut self.channel.rx,
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&mut self.channel.rx,
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@ -1116,6 +1117,8 @@ mod dma {
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unsafe {
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unsafe {
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self.dma_driver().start_transfer_dma(
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self.dma_driver().start_transfer_dma(
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false,
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false,
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0,
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bytes_to_write,
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&mut EmptyBuf,
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&mut EmptyBuf,
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&mut self.address_buffer,
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&mut self.address_buffer,
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&mut self.channel.rx,
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&mut self.channel.rx,
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@ -1275,8 +1278,12 @@ mod dma {
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/// The caller must ensure that the buffers are not accessed while the
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/// The caller must ensure that the buffers are not accessed while the
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/// transfer is in progress. Moving the buffers is allowed.
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/// transfer is in progress. Moving the buffers is allowed.
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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unsafe fn start_dma_write(&mut self, buffer: &mut impl DmaTxBuffer) -> Result<(), Error> {
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unsafe fn start_dma_write(
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self.start_dma_transfer(&mut EmptyBuf, buffer)
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&mut self,
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bytes_to_write: usize,
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buffer: &mut impl DmaTxBuffer,
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) -> Result<(), Error> {
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self.start_dma_transfer(0, bytes_to_write, &mut EmptyBuf, buffer)
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}
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}
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/// Perform a DMA write.
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/// Perform a DMA write.
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@ -1288,11 +1295,12 @@ mod dma {
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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pub fn write<TX: DmaTxBuffer>(
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pub fn write<TX: DmaTxBuffer>(
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mut self,
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mut self,
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bytes_to_write: usize,
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mut buffer: TX,
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mut buffer: TX,
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) -> Result<SpiDmaTransfer<'d, M, TX, T>, (Error, Self, TX)> {
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) -> Result<SpiDmaTransfer<'d, M, TX, T>, (Error, Self, TX)> {
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self.wait_for_idle();
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self.wait_for_idle();
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match unsafe { self.start_dma_write(&mut buffer) } {
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match unsafe { self.start_dma_write(bytes_to_write, &mut buffer) } {
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Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
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Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
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Err(e) => Err((e, self, buffer)),
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Err(e) => Err((e, self, buffer)),
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}
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}
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@ -1303,8 +1311,12 @@ mod dma {
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/// The caller must ensure that the buffers are not accessed while the
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/// The caller must ensure that the buffers are not accessed while the
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/// transfer is in progress. Moving the buffers is allowed.
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/// transfer is in progress. Moving the buffers is allowed.
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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unsafe fn start_dma_read(&mut self, buffer: &mut impl DmaRxBuffer) -> Result<(), Error> {
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unsafe fn start_dma_read(
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self.start_dma_transfer(buffer, &mut EmptyBuf)
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&mut self,
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bytes_to_read: usize,
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buffer: &mut impl DmaRxBuffer,
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) -> Result<(), Error> {
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self.start_dma_transfer(bytes_to_read, 0, buffer, &mut EmptyBuf)
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}
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}
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/// Perform a DMA read.
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/// Perform a DMA read.
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@ -1316,10 +1328,11 @@ mod dma {
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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pub fn read<RX: DmaRxBuffer>(
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pub fn read<RX: DmaRxBuffer>(
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mut self,
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mut self,
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bytes_to_read: usize,
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mut buffer: RX,
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mut buffer: RX,
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) -> Result<SpiDmaTransfer<'d, M, RX, T>, (Error, Self, RX)> {
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) -> Result<SpiDmaTransfer<'d, M, RX, T>, (Error, Self, RX)> {
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self.wait_for_idle();
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self.wait_for_idle();
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match unsafe { self.start_dma_read(&mut buffer) } {
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match unsafe { self.start_dma_read(bytes_to_read, &mut buffer) } {
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Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
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Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
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Err(e) => Err((e, self, buffer)),
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Err(e) => Err((e, self, buffer)),
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}
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}
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@ -1332,10 +1345,12 @@ mod dma {
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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unsafe fn start_dma_transfer(
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unsafe fn start_dma_transfer(
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&mut self,
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&mut self,
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bytes_to_read: usize,
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bytes_to_write: usize,
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rx_buffer: &mut impl DmaRxBuffer,
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rx_buffer: &mut impl DmaRxBuffer,
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tx_buffer: &mut impl DmaTxBuffer,
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tx_buffer: &mut impl DmaTxBuffer,
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) -> Result<(), Error> {
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) -> Result<(), Error> {
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self.start_transfer_dma(true, rx_buffer, tx_buffer)
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self.start_transfer_dma(true, bytes_to_read, bytes_to_write, rx_buffer, tx_buffer)
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}
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}
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/// Perform a DMA transfer
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/// Perform a DMA transfer
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@ -1347,11 +1362,20 @@ mod dma {
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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#[cfg_attr(place_spi_driver_in_ram, ram)]
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pub fn transfer<RX: DmaRxBuffer, TX: DmaTxBuffer>(
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pub fn transfer<RX: DmaRxBuffer, TX: DmaTxBuffer>(
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mut self,
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mut self,
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bytes_to_read: usize,
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mut rx_buffer: RX,
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mut rx_buffer: RX,
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bytes_to_write: usize,
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mut tx_buffer: TX,
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mut tx_buffer: TX,
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) -> Result<SpiDmaTransfer<'d, M, (RX, TX), T>, (Error, Self, RX, TX)> {
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) -> Result<SpiDmaTransfer<'d, M, (RX, TX), T>, (Error, Self, RX, TX)> {
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self.wait_for_idle();
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self.wait_for_idle();
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match unsafe { self.start_dma_transfer(&mut rx_buffer, &mut tx_buffer) } {
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match unsafe {
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self.start_dma_transfer(
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bytes_to_read,
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bytes_to_write,
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&mut rx_buffer,
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&mut tx_buffer,
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)
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} {
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Ok(_) => Ok(SpiDmaTransfer::new(self, (rx_buffer, tx_buffer))),
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Ok(_) => Ok(SpiDmaTransfer::new(self, (rx_buffer, tx_buffer))),
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Err(e) => Err((e, self, rx_buffer, tx_buffer)),
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Err(e) => Err((e, self, rx_buffer, tx_buffer)),
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}
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}
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@ -1368,10 +1392,9 @@ mod dma {
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cmd: Command,
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cmd: Command,
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address: Address,
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address: Address,
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dummy: u8,
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dummy: u8,
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bytes_to_read: usize,
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buffer: &mut impl DmaRxBuffer,
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buffer: &mut impl DmaRxBuffer,
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) -> Result<(), Error> {
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) -> Result<(), Error> {
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let bytes_to_read = buffer.length();
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self.driver().setup_half_duplex(
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self.driver().setup_half_duplex(
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false,
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false,
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cmd,
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cmd,
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@ -1382,7 +1405,7 @@ mod dma {
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data_mode,
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data_mode,
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);
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);
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self.start_transfer_dma(false, buffer, &mut EmptyBuf)
|
self.start_transfer_dma(false, bytes_to_read, 0, buffer, &mut EmptyBuf)
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Perform a half-duplex read operation using DMA.
|
/// Perform a half-duplex read operation using DMA.
|
||||||
@ -1394,12 +1417,20 @@ mod dma {
|
|||||||
cmd: Command,
|
cmd: Command,
|
||||||
address: Address,
|
address: Address,
|
||||||
dummy: u8,
|
dummy: u8,
|
||||||
|
bytes_to_read: usize,
|
||||||
mut buffer: RX,
|
mut buffer: RX,
|
||||||
) -> Result<SpiDmaTransfer<'d, M, RX, T>, (Error, Self, RX)> {
|
) -> Result<SpiDmaTransfer<'d, M, RX, T>, (Error, Self, RX)> {
|
||||||
self.wait_for_idle();
|
self.wait_for_idle();
|
||||||
|
|
||||||
match unsafe {
|
match unsafe {
|
||||||
self.start_half_duplex_read(data_mode, cmd, address, dummy, &mut buffer)
|
self.start_half_duplex_read(
|
||||||
|
data_mode,
|
||||||
|
cmd,
|
||||||
|
address,
|
||||||
|
dummy,
|
||||||
|
bytes_to_read,
|
||||||
|
&mut buffer,
|
||||||
|
)
|
||||||
} {
|
} {
|
||||||
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
|
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
|
||||||
Err(e) => Err((e, self, buffer)),
|
Err(e) => Err((e, self, buffer)),
|
||||||
@ -1417,10 +1448,9 @@ mod dma {
|
|||||||
cmd: Command,
|
cmd: Command,
|
||||||
address: Address,
|
address: Address,
|
||||||
dummy: u8,
|
dummy: u8,
|
||||||
|
bytes_to_write: usize,
|
||||||
buffer: &mut impl DmaTxBuffer,
|
buffer: &mut impl DmaTxBuffer,
|
||||||
) -> Result<(), Error> {
|
) -> Result<(), Error> {
|
||||||
let bytes_to_write = buffer.length();
|
|
||||||
|
|
||||||
#[cfg(all(esp32, spi_address_workaround))]
|
#[cfg(all(esp32, spi_address_workaround))]
|
||||||
{
|
{
|
||||||
// On the ESP32, if we don't have data, the address is always sent
|
// On the ESP32, if we don't have data, the address is always sent
|
||||||
@ -1440,7 +1470,7 @@ mod dma {
|
|||||||
data_mode,
|
data_mode,
|
||||||
);
|
);
|
||||||
|
|
||||||
self.start_transfer_dma(false, &mut EmptyBuf, buffer)
|
self.start_transfer_dma(false, 0, bytes_to_write, &mut EmptyBuf, buffer)
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Perform a half-duplex write operation using DMA.
|
/// Perform a half-duplex write operation using DMA.
|
||||||
@ -1452,12 +1482,20 @@ mod dma {
|
|||||||
cmd: Command,
|
cmd: Command,
|
||||||
address: Address,
|
address: Address,
|
||||||
dummy: u8,
|
dummy: u8,
|
||||||
|
bytes_to_write: usize,
|
||||||
mut buffer: TX,
|
mut buffer: TX,
|
||||||
) -> Result<SpiDmaTransfer<'d, M, TX, T>, (Error, Self, TX)> {
|
) -> Result<SpiDmaTransfer<'d, M, TX, T>, (Error, Self, TX)> {
|
||||||
self.wait_for_idle();
|
self.wait_for_idle();
|
||||||
|
|
||||||
match unsafe {
|
match unsafe {
|
||||||
self.start_half_duplex_write(data_mode, cmd, address, dummy, &mut buffer)
|
self.start_half_duplex_write(
|
||||||
|
data_mode,
|
||||||
|
cmd,
|
||||||
|
address,
|
||||||
|
dummy,
|
||||||
|
bytes_to_write,
|
||||||
|
&mut buffer,
|
||||||
|
)
|
||||||
} {
|
} {
|
||||||
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
|
Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)),
|
||||||
Err(e) => Err((e, self, buffer)),
|
Err(e) => Err((e, self, buffer)),
|
||||||
@ -1590,8 +1628,12 @@ mod dma {
|
|||||||
self.rx_buf.set_length(chunk.len());
|
self.rx_buf.set_length(chunk.len());
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
self.spi_dma
|
self.spi_dma.start_dma_transfer(
|
||||||
.start_dma_transfer(&mut self.rx_buf, &mut EmptyBuf)?;
|
chunk.len(),
|
||||||
|
0,
|
||||||
|
&mut self.rx_buf,
|
||||||
|
&mut EmptyBuf,
|
||||||
|
)?;
|
||||||
}
|
}
|
||||||
|
|
||||||
self.wait_for_idle();
|
self.wait_for_idle();
|
||||||
@ -1610,8 +1652,12 @@ mod dma {
|
|||||||
self.tx_buf.fill(chunk);
|
self.tx_buf.fill(chunk);
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
self.spi_dma
|
self.spi_dma.start_dma_transfer(
|
||||||
.start_dma_transfer(&mut EmptyBuf, &mut self.tx_buf)?;
|
chunk.len(),
|
||||||
|
0,
|
||||||
|
&mut EmptyBuf,
|
||||||
|
&mut self.tx_buf,
|
||||||
|
)?;
|
||||||
}
|
}
|
||||||
|
|
||||||
self.wait_for_idle();
|
self.wait_for_idle();
|
||||||
@ -1637,8 +1683,12 @@ mod dma {
|
|||||||
self.rx_buf.set_length(read_chunk.len());
|
self.rx_buf.set_length(read_chunk.len());
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
self.spi_dma
|
self.spi_dma.start_dma_transfer(
|
||||||
.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
|
read_chunk.len(),
|
||||||
|
write_chunk.len(),
|
||||||
|
&mut self.rx_buf,
|
||||||
|
&mut self.tx_buf,
|
||||||
|
)?;
|
||||||
}
|
}
|
||||||
self.wait_for_idle();
|
self.wait_for_idle();
|
||||||
|
|
||||||
@ -1665,8 +1715,12 @@ mod dma {
|
|||||||
self.rx_buf.set_length(chunk.len());
|
self.rx_buf.set_length(chunk.len());
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
self.spi_dma
|
self.spi_dma.start_dma_transfer(
|
||||||
.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
|
chunk.len(),
|
||||||
|
chunk.len(),
|
||||||
|
&mut self.rx_buf,
|
||||||
|
&mut self.tx_buf,
|
||||||
|
)?;
|
||||||
}
|
}
|
||||||
self.wait_for_idle();
|
self.wait_for_idle();
|
||||||
|
|
||||||
@ -1698,6 +1752,7 @@ mod dma {
|
|||||||
cmd,
|
cmd,
|
||||||
address,
|
address,
|
||||||
dummy,
|
dummy,
|
||||||
|
buffer.len(),
|
||||||
&mut self.rx_buf,
|
&mut self.rx_buf,
|
||||||
)?;
|
)?;
|
||||||
}
|
}
|
||||||
@ -1731,6 +1786,7 @@ mod dma {
|
|||||||
cmd,
|
cmd,
|
||||||
address,
|
address,
|
||||||
dummy,
|
dummy,
|
||||||
|
buffer.len(),
|
||||||
&mut self.tx_buf,
|
&mut self.tx_buf,
|
||||||
)?;
|
)?;
|
||||||
}
|
}
|
||||||
@ -1816,7 +1872,9 @@ mod dma {
|
|||||||
|
|
||||||
let mut spi = DropGuard::new(&mut self.spi_dma, |spi| spi.cancel_transfer());
|
let mut spi = DropGuard::new(&mut self.spi_dma, |spi| spi.cancel_transfer());
|
||||||
|
|
||||||
unsafe { spi.start_dma_transfer(&mut self.rx_buf, &mut EmptyBuf)? };
|
unsafe {
|
||||||
|
spi.start_dma_transfer(chunk.len(), 0, &mut self.rx_buf, &mut EmptyBuf)?
|
||||||
|
};
|
||||||
|
|
||||||
spi.wait_for_idle_async().await;
|
spi.wait_for_idle_async().await;
|
||||||
|
|
||||||
@ -1839,7 +1897,9 @@ mod dma {
|
|||||||
for chunk in words.chunks(chunk_size) {
|
for chunk in words.chunks(chunk_size) {
|
||||||
self.tx_buf.fill(chunk);
|
self.tx_buf.fill(chunk);
|
||||||
|
|
||||||
unsafe { spi.start_dma_transfer(&mut EmptyBuf, &mut self.tx_buf)? };
|
unsafe {
|
||||||
|
spi.start_dma_transfer(0, chunk.len(), &mut EmptyBuf, &mut self.tx_buf)?
|
||||||
|
};
|
||||||
|
|
||||||
spi.wait_for_idle_async().await;
|
spi.wait_for_idle_async().await;
|
||||||
}
|
}
|
||||||
@ -1872,7 +1932,12 @@ mod dma {
|
|||||||
self.rx_buf.set_length(read_chunk.len());
|
self.rx_buf.set_length(read_chunk.len());
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
spi.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
|
spi.start_dma_transfer(
|
||||||
|
read_chunk.len(),
|
||||||
|
write_chunk.len(),
|
||||||
|
&mut self.rx_buf,
|
||||||
|
&mut self.tx_buf,
|
||||||
|
)?;
|
||||||
}
|
}
|
||||||
spi.wait_for_idle_async().await;
|
spi.wait_for_idle_async().await;
|
||||||
|
|
||||||
@ -1902,7 +1967,12 @@ mod dma {
|
|||||||
self.rx_buf.set_length(chunk.len());
|
self.rx_buf.set_length(chunk.len());
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
spi.start_dma_transfer(&mut self.rx_buf, &mut self.tx_buf)?;
|
spi.start_dma_transfer(
|
||||||
|
chunk.len(),
|
||||||
|
chunk.len(),
|
||||||
|
&mut self.rx_buf,
|
||||||
|
&mut self.tx_buf,
|
||||||
|
)?;
|
||||||
}
|
}
|
||||||
spi.wait_for_idle_async().await;
|
spi.wait_for_idle_async().await;
|
||||||
|
|
||||||
@ -2147,10 +2217,13 @@ impl DmaDriver {
|
|||||||
self.info.update();
|
self.info.update();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[allow(clippy::too_many_arguments)]
|
||||||
#[cfg_attr(place_spi_driver_in_ram, ram)]
|
#[cfg_attr(place_spi_driver_in_ram, ram)]
|
||||||
unsafe fn start_transfer_dma<RX: Rx, TX: Tx>(
|
unsafe fn start_transfer_dma<RX: Rx, TX: Tx>(
|
||||||
&self,
|
&self,
|
||||||
_full_duplex: bool,
|
_full_duplex: bool,
|
||||||
|
rx_len: usize,
|
||||||
|
tx_len: usize,
|
||||||
rx_buffer: &mut impl DmaRxBuffer,
|
rx_buffer: &mut impl DmaRxBuffer,
|
||||||
tx_buffer: &mut impl DmaTxBuffer,
|
tx_buffer: &mut impl DmaTxBuffer,
|
||||||
rx: &mut RX,
|
rx: &mut RX,
|
||||||
@ -2165,8 +2238,6 @@ impl DmaDriver {
|
|||||||
reg_block.dma_in_link().write(|w| w.bits(0));
|
reg_block.dma_in_link().write(|w| w.bits(0));
|
||||||
}
|
}
|
||||||
|
|
||||||
let rx_len = rx_buffer.length();
|
|
||||||
let tx_len = tx_buffer.length();
|
|
||||||
self.info.configure_datalen(rx_len, tx_len);
|
self.info.configure_datalen(rx_len, tx_len);
|
||||||
|
|
||||||
// enable the MISO and MOSI if needed
|
// enable the MISO and MOSI if needed
|
||||||
|
|||||||
@ -115,7 +115,7 @@ fn main() -> ! {
|
|||||||
i = i.wrapping_add(1);
|
i = i.wrapping_add(1);
|
||||||
|
|
||||||
let transfer = spi
|
let transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
|
|
||||||
|
|||||||
@ -53,7 +53,14 @@ fn transfer_read(
|
|||||||
command: Command,
|
command: Command,
|
||||||
) -> (SpiUnderTest, DmaRxBuf) {
|
) -> (SpiUnderTest, DmaRxBuf) {
|
||||||
let transfer = spi
|
let transfer = spi
|
||||||
.half_duplex_read(SpiDataMode::Quad, command, Address::None, 0, dma_rx_buf)
|
.half_duplex_read(
|
||||||
|
SpiDataMode::Quad,
|
||||||
|
command,
|
||||||
|
Address::None,
|
||||||
|
0,
|
||||||
|
dma_rx_buf.len(),
|
||||||
|
dma_rx_buf,
|
||||||
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
transfer.wait()
|
transfer.wait()
|
||||||
@ -74,6 +81,7 @@ fn transfer_write(
|
|||||||
SpiDataMode::Quad,
|
SpiDataMode::Quad,
|
||||||
),
|
),
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
|
|||||||
@ -208,11 +208,17 @@ mod tests {
|
|||||||
|
|
||||||
for i in 1..4 {
|
for i in 1..4 {
|
||||||
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
|
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
|
||||||
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
|
let transfer = spi
|
||||||
|
.read(dma_rx_buf.len(), dma_rx_buf)
|
||||||
|
.map_err(|e| e.0)
|
||||||
|
.unwrap();
|
||||||
(spi, dma_rx_buf) = transfer.wait();
|
(spi, dma_rx_buf) = transfer.wait();
|
||||||
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
|
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
|
||||||
|
|
||||||
let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
|
let transfer = spi
|
||||||
|
.write(dma_tx_buf.len(), dma_tx_buf)
|
||||||
|
.map_err(|e| e.0)
|
||||||
|
.unwrap();
|
||||||
(spi, dma_tx_buf) = transfer.wait();
|
(spi, dma_tx_buf) = transfer.wait();
|
||||||
assert_eq!(unit.value(), (i * 3 * DMA_BUFFER_SIZE) as _);
|
assert_eq!(unit.value(), (i * 3 * DMA_BUFFER_SIZE) as _);
|
||||||
}
|
}
|
||||||
@ -239,12 +245,15 @@ mod tests {
|
|||||||
|
|
||||||
for i in 1..4 {
|
for i in 1..4 {
|
||||||
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
|
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
|
||||||
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
|
let transfer = spi
|
||||||
|
.read(dma_rx_buf.len(), dma_rx_buf)
|
||||||
|
.map_err(|e| e.0)
|
||||||
|
.unwrap();
|
||||||
(spi, dma_rx_buf) = transfer.wait();
|
(spi, dma_rx_buf) = transfer.wait();
|
||||||
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
|
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
|
||||||
|
|
||||||
let transfer = spi
|
let transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
|
(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
|
||||||
@ -269,7 +278,7 @@ mod tests {
|
|||||||
dma_tx_buf.as_mut_slice()[0] = i as u8;
|
dma_tx_buf.as_mut_slice()[0] = i as u8;
|
||||||
*dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
|
*dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
|
||||||
let transfer = spi
|
let transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
|
|
||||||
@ -293,7 +302,7 @@ mod tests {
|
|||||||
|
|
||||||
let spi = ctx.spi.with_dma(ctx.dma_channel);
|
let spi = ctx.spi.with_dma(ctx.dma_channel);
|
||||||
let transfer = spi
|
let transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
let (spi, (dma_rx_buf, mut dma_tx_buf)) = transfer.wait();
|
let (spi, (dma_rx_buf, mut dma_tx_buf)) = transfer.wait();
|
||||||
@ -304,7 +313,7 @@ mod tests {
|
|||||||
dma_tx_buf.fill(&[0xaa, 0xdd, 0xef, 0xbe]);
|
dma_tx_buf.fill(&[0xaa, 0xdd, 0xef, 0xbe]);
|
||||||
|
|
||||||
let transfer = spi
|
let transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
|
let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
|
||||||
@ -458,18 +467,30 @@ mod tests {
|
|||||||
|
|
||||||
dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
|
dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
|
||||||
|
|
||||||
let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
|
let transfer = spi
|
||||||
|
.write(dma_tx_buf.len(), dma_tx_buf)
|
||||||
|
.map_err(|e| e.0)
|
||||||
|
.unwrap();
|
||||||
let (spi, dma_tx_buf) = transfer.wait();
|
let (spi, dma_tx_buf) = transfer.wait();
|
||||||
|
|
||||||
dma_rx_buf.as_mut_slice().fill(0);
|
dma_rx_buf.as_mut_slice().fill(0);
|
||||||
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
|
let transfer = spi
|
||||||
|
.read(dma_rx_buf.len(), dma_rx_buf)
|
||||||
|
.map_err(|e| e.0)
|
||||||
|
.unwrap();
|
||||||
let (spi, mut dma_rx_buf) = transfer.wait();
|
let (spi, mut dma_rx_buf) = transfer.wait();
|
||||||
|
|
||||||
let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
|
let transfer = spi
|
||||||
|
.write(dma_tx_buf.len(), dma_tx_buf)
|
||||||
|
.map_err(|e| e.0)
|
||||||
|
.unwrap();
|
||||||
let (spi, _dma_tx_buf) = transfer.wait();
|
let (spi, _dma_tx_buf) = transfer.wait();
|
||||||
|
|
||||||
dma_rx_buf.as_mut_slice().fill(0);
|
dma_rx_buf.as_mut_slice().fill(0);
|
||||||
let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
|
let transfer = spi
|
||||||
|
.read(dma_rx_buf.len(), dma_rx_buf)
|
||||||
|
.map_err(|e| e.0)
|
||||||
|
.unwrap();
|
||||||
let (_, dma_rx_buf) = transfer.wait();
|
let (_, dma_rx_buf) = transfer.wait();
|
||||||
|
|
||||||
assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
|
assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
|
||||||
@ -492,7 +513,7 @@ mod tests {
|
|||||||
let spi = ctx.spi.with_dma(ctx.dma_channel);
|
let spi = ctx.spi.with_dma(ctx.dma_channel);
|
||||||
|
|
||||||
let mut transfer = spi
|
let mut transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
|
|
||||||
@ -515,7 +536,7 @@ mod tests {
|
|||||||
let mut spi = ctx.spi.with_dma(ctx.dma_channel);
|
let mut spi = ctx.spi.with_dma(ctx.dma_channel);
|
||||||
|
|
||||||
let mut transfer = spi
|
let mut transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
|
|
||||||
@ -526,7 +547,7 @@ mod tests {
|
|||||||
.unwrap();
|
.unwrap();
|
||||||
|
|
||||||
let transfer = spi
|
let transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
|
|
||||||
@ -548,7 +569,7 @@ mod tests {
|
|||||||
let spi = ctx.spi.with_dma(ctx.dma_channel).into_async();
|
let spi = ctx.spi.with_dma(ctx.dma_channel).into_async();
|
||||||
|
|
||||||
let mut transfer = spi
|
let mut transfer = spi
|
||||||
.transfer(dma_rx_buf, dma_tx_buf)
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
|
|
||||||
|
|||||||
@ -79,6 +79,7 @@ mod tests {
|
|||||||
Command::None,
|
Command::None,
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
dma_rx_buf.len(),
|
||||||
dma_rx_buf,
|
dma_rx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
@ -96,6 +97,7 @@ mod tests {
|
|||||||
Command::None,
|
Command::None,
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
dma_rx_buf.len(),
|
||||||
dma_rx_buf,
|
dma_rx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
|
|||||||
@ -92,6 +92,7 @@ mod tests {
|
|||||||
Command::None,
|
Command::None,
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
@ -106,6 +107,7 @@ mod tests {
|
|||||||
Command::None,
|
Command::None,
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
|
|||||||
@ -107,6 +107,7 @@ mod tests {
|
|||||||
Command::None,
|
Command::None,
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
@ -121,6 +122,7 @@ mod tests {
|
|||||||
Command::None,
|
Command::None,
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
|
|||||||
@ -100,6 +100,7 @@ fn main() -> ! {
|
|||||||
Command::Command8(0x06, SpiDataMode::Single),
|
Command::Command8(0x06, SpiDataMode::Single),
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
0,
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
@ -114,6 +115,7 @@ fn main() -> ! {
|
|||||||
Command::Command8(0x20, SpiDataMode::Single),
|
Command::Command8(0x20, SpiDataMode::Single),
|
||||||
Address::Address24(0x000000, SpiDataMode::Single),
|
Address::Address24(0x000000, SpiDataMode::Single),
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
@ -128,6 +130,7 @@ fn main() -> ! {
|
|||||||
Command::Command8(0x06, SpiDataMode::Single),
|
Command::Command8(0x06, SpiDataMode::Single),
|
||||||
Address::None,
|
Address::None,
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
@ -145,6 +148,7 @@ fn main() -> ! {
|
|||||||
Command::Command8(0x32, SpiDataMode::Single),
|
Command::Command8(0x32, SpiDataMode::Single),
|
||||||
Address::Address24(0x000000, SpiDataMode::Single),
|
Address::Address24(0x000000, SpiDataMode::Single),
|
||||||
0,
|
0,
|
||||||
|
dma_tx_buf.len(),
|
||||||
dma_tx_buf,
|
dma_tx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
@ -160,6 +164,7 @@ fn main() -> ! {
|
|||||||
Command::Command8(0xeb, SpiDataMode::Single),
|
Command::Command8(0xeb, SpiDataMode::Single),
|
||||||
Address::Address32(0x000000 << 8, SpiDataMode::Quad),
|
Address::Address32(0x000000 << 8, SpiDataMode::Quad),
|
||||||
4,
|
4,
|
||||||
|
dma_rx_buf.len(),
|
||||||
dma_rx_buf,
|
dma_rx_buf,
|
||||||
)
|
)
|
||||||
.map_err(|e| e.0)
|
.map_err(|e| e.0)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user