Fix various SPI/DMA issues (#2065)
* Add failing test * Fix enabled interrupt * Fix using the correct waker * Changelog * Enable test on more devices that have SPI3
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08d406ee2b
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9465244e0d
@ -16,6 +16,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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### Fixed
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### Fixed
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- Fixed an issue with DMA transfers potentially not waking up the correct async task (#2065)
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### Removed
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### Removed
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## [0.20.1] - 2024-08-30
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## [0.20.1] - 2024-08-30
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@ -420,14 +420,25 @@ impl<const N: u8> RegisterAccess for Channel<N> {
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#[doc(hidden)]
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#[doc(hidden)]
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pub struct ChannelTxImpl<const N: u8> {}
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pub struct ChannelTxImpl<const N: u8> {}
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#[cfg(feature = "async")]
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use embassy_sync::waitqueue::AtomicWaker;
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#[cfg(feature = "async")]
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#[allow(clippy::declare_interior_mutable_const)]
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const INIT: AtomicWaker = AtomicWaker::new();
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#[cfg(feature = "async")]
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static TX_WAKERS: [AtomicWaker; CHANNEL_COUNT] = [INIT; CHANNEL_COUNT];
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#[cfg(feature = "async")]
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static RX_WAKERS: [AtomicWaker; CHANNEL_COUNT] = [INIT; CHANNEL_COUNT];
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impl<const N: u8> crate::private::Sealed for ChannelTxImpl<N> {}
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impl<const N: u8> crate::private::Sealed for ChannelTxImpl<N> {}
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impl<const N: u8> TxChannel<Channel<N>> for ChannelTxImpl<N> {
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impl<const N: u8> TxChannel<Channel<N>> for ChannelTxImpl<N> {
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#[cfg(feature = "async")]
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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fn waker() -> &'static AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker =
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&TX_WAKERS[N as usize]
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embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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}
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}
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@ -439,10 +450,8 @@ impl<const N: u8> crate::private::Sealed for ChannelRxImpl<N> {}
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impl<const N: u8> RxChannel<Channel<N>> for ChannelRxImpl<N> {
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impl<const N: u8> RxChannel<Channel<N>> for ChannelRxImpl<N> {
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#[cfg(feature = "async")]
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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fn waker() -> &'static AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker =
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&RX_WAKERS[N as usize]
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embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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}
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}
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@ -569,16 +578,24 @@ macro_rules! impl_channel {
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cfg_if::cfg_if! {
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cfg_if::cfg_if! {
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if #[cfg(esp32c2)] {
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if #[cfg(esp32c2)] {
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#[cfg(feature = "async")]
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const CHANNEL_COUNT: usize = 1;
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_CH0);
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_CH0);
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} else if #[cfg(esp32c3)] {
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} else if #[cfg(esp32c3)] {
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#[cfg(feature = "async")]
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const CHANNEL_COUNT: usize = 3;
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_CH0);
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_CH0);
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impl_channel!(1, super::asynch::interrupt::interrupt_handler_ch1, DMA_CH1);
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impl_channel!(1, super::asynch::interrupt::interrupt_handler_ch1, DMA_CH1);
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impl_channel!(2, super::asynch::interrupt::interrupt_handler_ch2, DMA_CH2);
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impl_channel!(2, super::asynch::interrupt::interrupt_handler_ch2, DMA_CH2);
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} else if #[cfg(any(esp32c6, esp32h2))] {
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} else if #[cfg(any(esp32c6, esp32h2))] {
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#[cfg(feature = "async")]
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const CHANNEL_COUNT: usize = 3;
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_IN_CH0, DMA_OUT_CH0);
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_IN_CH0, DMA_OUT_CH0);
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impl_channel!(1, super::asynch::interrupt::interrupt_handler_ch1, DMA_IN_CH1, DMA_OUT_CH1);
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impl_channel!(1, super::asynch::interrupt::interrupt_handler_ch1, DMA_IN_CH1, DMA_OUT_CH1);
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impl_channel!(2, super::asynch::interrupt::interrupt_handler_ch2, DMA_IN_CH2, DMA_OUT_CH2);
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impl_channel!(2, super::asynch::interrupt::interrupt_handler_ch2, DMA_IN_CH2, DMA_OUT_CH2);
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} else if #[cfg(esp32s3)] {
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} else if #[cfg(esp32s3)] {
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#[cfg(feature = "async")]
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const CHANNEL_COUNT: usize = 5;
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_IN_CH0, DMA_OUT_CH0);
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impl_channel!(0, super::asynch::interrupt::interrupt_handler_ch0, DMA_IN_CH0, DMA_OUT_CH0);
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impl_channel!(1, super::asynch::interrupt::interrupt_handler_ch1, DMA_IN_CH1, DMA_OUT_CH1);
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impl_channel!(1, super::asynch::interrupt::interrupt_handler_ch1, DMA_IN_CH1, DMA_OUT_CH1);
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impl_channel!(2, super::asynch::interrupt::interrupt_handler_ch2, DMA_IN_CH2, DMA_OUT_CH2);
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impl_channel!(2, super::asynch::interrupt::interrupt_handler_ch2, DMA_IN_CH2, DMA_OUT_CH2);
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@ -3661,7 +3661,7 @@ impl Instance for crate::peripherals::SPI3 {
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#[inline(always)]
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#[inline(always)]
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fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
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fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
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self.bind_spi3_interrupt(handler.handler());
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self.bind_spi3_interrupt(handler.handler());
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crate::interrupt::enable(crate::peripherals::Interrupt::SPI2, handler.priority()).unwrap();
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crate::interrupt::enable(crate::peripherals::Interrupt::SPI3, handler.priority()).unwrap();
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}
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}
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#[inline(always)]
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#[inline(always)]
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@ -3792,7 +3792,7 @@ impl Instance for crate::peripherals::SPI3 {
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#[inline(always)]
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#[inline(always)]
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fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
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fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
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self.bind_spi3_interrupt(handler.handler());
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self.bind_spi3_interrupt(handler.handler());
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crate::interrupt::enable(crate::peripherals::Interrupt::SPI2, handler.priority()).unwrap();
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crate::interrupt::enable(crate::peripherals::Interrupt::SPI3, handler.priority()).unwrap();
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}
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}
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#[inline(always)]
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#[inline(always)]
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@ -158,6 +158,11 @@ name = "embassy_interrupt_executor"
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harness = false
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harness = false
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required-features = ["async", "embassy"]
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required-features = ["async", "embassy"]
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[[test]]
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name = "embassy_interrupt_spi_dma"
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harness = false
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required-features = ["async", "embassy"]
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[[test]]
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[[test]]
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name = "twai"
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name = "twai"
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harness = false
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harness = false
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130
hil-test/tests/embassy_interrupt_spi_dma.rs
Normal file
130
hil-test/tests/embassy_interrupt_spi_dma.rs
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@ -0,0 +1,130 @@
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//! Reproduction and regression test for a sneaky issue.
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//% CHIPS: esp32 esp32s2 esp32s3
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//% FEATURES: integrated-timers
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//% FEATURES: generic-queue
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#![no_std]
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#![no_main]
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use embassy_time::{Duration, Instant, Ticker};
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use esp_hal::{
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dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
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dma_buffers,
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interrupt::{software::SoftwareInterruptControl, Priority},
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peripherals::SPI3,
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prelude::*,
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spi::{
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master::{Spi, SpiDma},
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FullDuplexMode,
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SpiMode,
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},
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timer::{timg::TimerGroup, ErasedTimer},
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Async,
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};
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use esp_hal_embassy::InterruptExecutor;
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use hil_test as _;
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cfg_if::cfg_if! {
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if #[cfg(any(
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feature = "esp32",
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feature = "esp32s2",
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))] {
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use esp_hal::dma::Spi3DmaChannel as DmaChannel1;
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} else {
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use esp_hal::dma::DmaChannel1;
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}
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}
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macro_rules! mk_static {
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($t:ty,$val:expr) => {{
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static STATIC_CELL: static_cell::StaticCell<$t> = static_cell::StaticCell::new();
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#[deny(unused_attributes)]
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let x = STATIC_CELL.uninit().write(($val));
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x
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}};
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}
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#[embassy_executor::task]
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async fn interrupt_driven_task(spi: SpiDma<'static, SPI3, DmaChannel1, FullDuplexMode, Async>) {
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let mut ticker = Ticker::every(Duration::from_millis(1));
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let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(128);
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut spi = spi.with_buffers(dma_tx_buf, dma_rx_buf);
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loop {
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let mut buffer: [u8; 8] = [0; 8];
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spi.transfer_in_place_async(&mut buffer).await.unwrap();
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ticker.next().await;
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}
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}
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#[cfg(test)]
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#[embedded_test::tests(executor = esp_hal_embassy::Executor::new())]
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mod test {
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use super::*;
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#[test]
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#[timeout(3)]
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async fn run_interrupt_executor_test() {
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let (peripherals, clocks) = esp_hal::init(esp_hal::Config::default());
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let timg0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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esp_hal_embassy::init(
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&clocks,
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[
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ErasedTimer::from(timg0.timer0),
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ErasedTimer::from(timg0.timer1),
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],
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);
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let dma = Dma::new(peripherals.DMA);
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
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let dma_channel1 = dma.spi2channel;
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let dma_channel2 = dma.spi3channel;
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} else {
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let dma_channel1 = dma.channel0;
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let dma_channel2 = dma.channel1;
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}
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}
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let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(1024);
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0, &clocks)
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.with_dma(dma_channel1.configure_for_async(false, DmaPriority::Priority0))
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.with_buffers(dma_tx_buf, dma_rx_buf);
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let spi2 = Spi::new(peripherals.SPI3, 100.kHz(), SpiMode::Mode0, &clocks)
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.with_dma(dma_channel2.configure_for_async(false, DmaPriority::Priority0));
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let sw_ints = SoftwareInterruptControl::new(peripherals.SW_INTERRUPT);
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let interrupt_executor = mk_static!(
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InterruptExecutor<1>,
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InterruptExecutor::new(sw_ints.software_interrupt1)
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);
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let spawner = interrupt_executor.start(Priority::Priority3);
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spawner.spawn(interrupt_driven_task(spi2)).unwrap();
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let start = Instant::now();
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let mut buffer: [u8; 1024] = [0; 1024];
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loop {
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spi.transfer_in_place_async(&mut buffer).await.unwrap();
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if start.elapsed() > Duration::from_secs(1) {
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break;
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}
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}
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}
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}
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