diff --git a/esp-hal/src/rsa/esp32.rs b/esp-hal/src/rsa/esp32.rs
index 3a68d61c4..e5070d601 100644
--- a/esp-hal/src/rsa/esp32.rs
+++ b/esp-hal/src/rsa/esp32.rs
@@ -12,11 +12,8 @@ impl<Dm: crate::DriverMode> Rsa<'_, Dm> {
     /// After the RSA Accelerator is released from reset, the memory blocks
     /// needs to be initialized, only after that peripheral should be used.
     /// This function would return without an error if the memory is initialized
-    pub fn ready(&mut self) -> Option<()> {
-        if self.rsa.clean().read().clean().bit_is_clear() {
-            return None;
-        }
-        Some(())
+    pub fn ready(&mut self) {
+        while !self.rsa.clean().read().clean().bit_is_clear() {}
     }
 
     /// Writes the multi-mode configuration to the RSA hardware.
diff --git a/esp-hal/src/rsa/esp32cX.rs b/esp-hal/src/rsa/esp32cX.rs
index fa403a1b8..a376e3962 100644
--- a/esp-hal/src/rsa/esp32cX.rs
+++ b/esp-hal/src/rsa/esp32cX.rs
@@ -12,11 +12,8 @@ impl<Dm: crate::DriverMode> Rsa<'_, Dm> {
     /// After the RSA Accelerator is released from reset, the memory blocks
     /// needs to be initialized, only after that peripheral should be used.
     /// This function would return without an error if the memory is initialized
-    pub fn ready(&mut self) -> Option<()> {
-        if self.rsa.query_clean().read().query_clean().bit_is_clear() {
-            return None;
-        }
-        Some(())
+    pub fn ready(&mut self) {
+        while !self.rsa.query_clean().read().query_clean().bit_is_clear() {}
     }
 
     /// Enables/disables rsa interrupt.
diff --git a/esp-hal/src/rsa/esp32sX.rs b/esp-hal/src/rsa/esp32sX.rs
index d9b881bac..4816d04a1 100644
--- a/esp-hal/src/rsa/esp32sX.rs
+++ b/esp-hal/src/rsa/esp32sX.rs
@@ -13,11 +13,8 @@ impl<Dm: crate::DriverMode> Rsa<'_, Dm> {
     /// needs to be initialized, only after that peripheral should be used.
     /// This function would return without an error if the memory is
     /// initialized.
-    pub fn ready(&mut self) -> Option<()> {
-        if self.rsa.clean().read().clean().bit_is_clear() {
-            return None;
-        }
-        Some(())
+    pub fn ready(&mut self) {
+        while !self.rsa.clean().read().clean().bit_is_clear() {}
     }
 
     /// Enables/disables rsa interrupt.
diff --git a/hil-test/tests/rsa.rs b/hil-test/tests/rsa.rs
index b4ff6a018..70d8e8596 100644
--- a/hil-test/tests/rsa.rs
+++ b/hil-test/tests/rsa.rs
@@ -56,7 +56,7 @@ mod tests {
     fn init() -> Context<'static> {
         let peripherals = esp_hal::init(esp_hal::Config::default());
         let mut rsa = Rsa::new(peripherals.RSA);
-        while rsa.ready().is_none() {}
+        rsa.ready();
 
         Context { rsa }
     }
diff --git a/hil-test/tests/rsa_async.rs b/hil-test/tests/rsa_async.rs
index 7b5a1cf63..7edeb005b 100644
--- a/hil-test/tests/rsa_async.rs
+++ b/hil-test/tests/rsa_async.rs
@@ -56,7 +56,7 @@ mod tests {
     fn init() -> Context<'static> {
         let peripherals = esp_hal::init(esp_hal::Config::default());
         let mut rsa = Rsa::new(peripherals.RSA).into_async();
-        while rsa.ready().is_none() {}
+        rsa.ready();
 
         Context { rsa }
     }