GetLitFam/esp-hal
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Stabilize CpuClock, make non-exhaustive, rename variants (#2899)

Browse Source 
* Stabilize CpuClock, make non-exhaustive, rename variants

* CHANGELOG.md

* Fix
This commit is contained in:
Björn Quentin 2025-01-07 15:43:41 +01:00 committed by GitHub
parent b3401bff59
commit 66d2effee2
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
14 changed files with 93 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
esp-hal/CHANGELOG.md
View File

@ -94,6 +94,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- UART: Make `AtCmdConfig` use builder-lite pattern (#2851) - UART: Make `AtCmdConfig` use builder-lite pattern (#2851)
- UART: Fix naming violations for `DataBits`, `Parity`, and `StopBits` enum variants (#2893) - UART: Fix naming violations for `DataBits`, `Parity`, and `StopBits` enum variants (#2893)
- UART: Remove blocking version of `read_bytes` and rename `drain_fifo` to `read_bytes` instead (#2895) - UART: Remove blocking version of `read_bytes` and rename `drain_fifo` to `read_bytes` instead (#2895)
- Renamed variants of `CpuClock`, made the enum non-exhaustive (#2899)
### Fixed ### Fixed

11
esp-hal/MIGRATING-0.22.md
View File

@ -394,3 +394,14 @@ Full duplex does not require this, and it also creates an artificial restriction
If you were using half duplex SPI with `with_miso`, If you were using half duplex SPI with `with_miso`,
you should now use `with_sio1` instead to get the previous behavior. you should now use `with_sio1` instead to get the previous behavior.
## CPU Clocks
The specific CPU clock variants are renamed from e.g. `Clock80MHz` to `_80MHz`.
```diff
- CpuClock::Clock80MHz
+ CpuClock::_80MHz
```
Additionally the enum is marked as non-exhaustive.

18
esp-hal/src/clock/clocks_ll/esp32.rs
View File

@ -64,7 +64,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
// Configure 320M PLL // Configure 320M PLL
match xtal_freq { match xtal_freq {
XtalClock::RtcXtalFreq40M => { XtalClock::_40M => {
div_ref = 0; div_ref = 0;
div7_0 = 32; div7_0 = 32;
div10_8 = 0; div10_8 = 0;
@ -73,7 +73,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 3; bw = 3;
} }
XtalClock::RtcXtalFreq26M => { XtalClock::_26M => {
div_ref = 12; div_ref = 12;
div7_0 = 224; div7_0 = 224;
div10_8 = 4; div10_8 = 4;
@ -82,7 +82,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 1; bw = 1;
} }
XtalClock::RtcXtalFreqOther(_) => { XtalClock::Other(_) => {
div_ref = 12; div_ref = 12;
div7_0 = 224; div7_0 = 224;
div10_8 = 4; div10_8 = 4;
@ -102,7 +102,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
// Configure 480M PLL // Configure 480M PLL
match xtal_freq { match xtal_freq {
XtalClock::RtcXtalFreq40M => { XtalClock::_40M => {
div_ref = 0; div_ref = 0;
div7_0 = 28; div7_0 = 28;
div10_8 = 0; div10_8 = 0;
@ -111,7 +111,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 3; bw = 3;
} }
XtalClock::RtcXtalFreq26M => { XtalClock::_26M => {
div_ref = 12; div_ref = 12;
div7_0 = 144; div7_0 = 144;
div10_8 = 4; div10_8 = 4;
@ -120,7 +120,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 1; bw = 1;
} }
XtalClock::RtcXtalFreqOther(_) => { XtalClock::Other(_) => {
div_ref = 12; div_ref = 12;
div7_0 = 224; div7_0 = 224;
div10_8 = 4; div10_8 = 4;
@ -220,14 +220,14 @@ pub(crate) fn set_cpu_freq(cpu_freq_mhz: crate::clock::CpuClock) {
let per_conf; let per_conf;
match cpu_freq_mhz { match cpu_freq_mhz {
crate::clock::CpuClock::Clock160MHz => { crate::clock::CpuClock::_160MHz => {
per_conf = CPU_160M; per_conf = CPU_160M;
} }
crate::clock::CpuClock::Clock240MHz => { crate::clock::CpuClock::_240MHz => {
dbias = dig_dbias_240_m; dbias = dig_dbias_240_m;
per_conf = CPU_240M; per_conf = CPU_240M;
} }
crate::clock::CpuClock::Clock80MHz => { crate::clock::CpuClock::_80MHz => {
per_conf = CPU_80M; per_conf = CPU_80M;
} }
} }

8
esp-hal/src/clock/clocks_ll/esp32c2.rs
View File

@ -65,7 +65,7 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
// Configure 480M PLL // Configure 480M PLL
match xtal_freq { match xtal_freq {
XtalClock::RtcXtalFreq26M => { XtalClock::_26M => {
div_ref = 12; div_ref = 12;
div7_0 = 236; div7_0 = 236;
dr1 = 4; dr1 = 4;
@ -74,7 +74,7 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
dcur = 0; dcur = 0;
dbias = 2; dbias = 2;
} }
XtalClock::RtcXtalFreq40M | XtalClock::RtcXtalFreqOther(_) => { XtalClock::_40M | XtalClock::Other(_) => {
div_ref = 0; div_ref = 0;
div7_0 = 8; div7_0 = 8;
dr1 = 0; dr1 = 0;
@ -150,8 +150,8 @@ pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
.modify(|_, w| w.pre_div_cnt().bits(0).soc_clk_sel().bits(1)); .modify(|_, w| w.pre_div_cnt().bits(0).soc_clk_sel().bits(1));
system_control.cpu_per_conf().modify(|_, w| { system_control.cpu_per_conf().modify(|_, w| {
w.cpuperiod_sel().bits(match cpu_clock_speed { w.cpuperiod_sel().bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0, CpuClock::_80MHz => 0,
CpuClock::Clock120MHz => 1, CpuClock::_120MHz => 1,
}) })
}); });
} }

16
esp-hal/src/clock/clocks_ll/esp32c3.rs
View File

@ -70,7 +70,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
// Configure 480M PLL // Configure 480M PLL
match xtal_freq { match xtal_freq {
XtalClock::RtcXtalFreq40M => { XtalClock::_40M => {
div_ref = 0; div_ref = 0;
div7_0 = 8; div7_0 = 8;
dr1 = 0; dr1 = 0;
@ -80,7 +80,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2; dbias = 2;
} }
XtalClock::RtcXtalFreq32M => { XtalClock::_32M => {
div_ref = 1; div_ref = 1;
div7_0 = 26; div7_0 = 26;
dr1 = 1; dr1 = 1;
@ -90,7 +90,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2; dbias = 2;
} }
XtalClock::RtcXtalFreqOther(_) => { XtalClock::Other(_) => {
div_ref = 0; div_ref = 0;
div7_0 = 8; div7_0 = 8;
dr1 = 0; dr1 = 0;
@ -110,7 +110,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
// Configure 320M PLL // Configure 320M PLL
match xtal_freq { match xtal_freq {
XtalClock::RtcXtalFreq40M => { XtalClock::_40M => {
div_ref = 0; div_ref = 0;
div7_0 = 4; div7_0 = 4;
dr1 = 0; dr1 = 0;
@ -120,7 +120,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2; dbias = 2;
} }
XtalClock::RtcXtalFreq32M => { XtalClock::_32M => {
div_ref = 1; div_ref = 1;
div7_0 = 6; div7_0 = 6;
dr1 = 0; dr1 = 0;
@ -130,7 +130,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2; dbias = 2;
} }
XtalClock::RtcXtalFreqOther(_) => { XtalClock::Other(_) => {
div_ref = 0; div_ref = 0;
div7_0 = 4; div7_0 = 4;
dr1 = 0; dr1 = 0;
@ -211,8 +211,8 @@ pub(crate) fn esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
.modify(|_, w| w.pre_div_cnt().bits(0).soc_clk_sel().bits(1)); .modify(|_, w| w.pre_div_cnt().bits(0).soc_clk_sel().bits(1));
system_control.cpu_per_conf().modify(|_, w| { system_control.cpu_per_conf().modify(|_, w| {
w.cpuperiod_sel().bits(match cpu_clock_speed { w.cpuperiod_sel().bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0, CpuClock::_80MHz => 0,
CpuClock::Clock160MHz => 1, CpuClock::_160MHz => 1,
}) })
}); });
} }

12
esp-hal/src/clock/clocks_ll/esp32s2.rs
View File

@ -23,17 +23,17 @@ pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) {
.set_bit() .set_bit()
.cpuperiod_sel() .cpuperiod_sel()
.bits(match cpu_clock_speed { .bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0, CpuClock::_80MHz => 0,
CpuClock::Clock160MHz => 1, CpuClock::_160MHz => 1,
CpuClock::Clock240MHz => 2, CpuClock::_240MHz => 2,
}) })
}); });
rtc_cntl.reg().modify(|_, w| { rtc_cntl.reg().modify(|_, w| {
w.dig_reg_dbias_wak().bits(match cpu_clock_speed { w.dig_reg_dbias_wak().bits(match cpu_clock_speed {
CpuClock::Clock80MHz => DIG_DBIAS_80M_160M, CpuClock::_80MHz => DIG_DBIAS_80M_160M,
CpuClock::Clock160MHz => DIG_DBIAS_80M_160M, CpuClock::_160MHz => DIG_DBIAS_80M_160M,
CpuClock::Clock240MHz => DIG_DBIAS_240M, CpuClock::_240MHz => DIG_DBIAS_240M,
} as u8) } as u8)
}); });

6
esp-hal/src/clock/clocks_ll/esp32s3.rs
View File

@ -17,9 +17,9 @@ pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) {
.set_bit() .set_bit()
.cpuperiod_sel() .cpuperiod_sel()
.bits(match cpu_clock_speed { .bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0, CpuClock::_80MHz => 0,
CpuClock::Clock160MHz => 1, CpuClock::_160MHz => 1,
CpuClock::Clock240MHz => 2, CpuClock::_240MHz => 2,
}) })
}); });
} }

74
esp-hal/src/clock/mod.rs
View File

@ -28,9 +28,7 @@
//! ### Frozen Clock Frequencies //! ### Frozen Clock Frequencies
//! //!
//! Once the clock configuration is applied, the clock frequencies become //! Once the clock configuration is applied, the clock frequencies become
//! `frozen` and cannot be changed. The `Clocks` struct is returned as part of //! `frozen` and cannot be changed.
//! the `System` struct, providing read-only access to the configured clock
//! frequencies.
//! //!
//! ## Examples //! ## Examples
//! //!
@ -60,6 +58,7 @@ use crate::rtc_cntl::RtcClock;
pub(crate) mod clocks_ll; pub(crate) mod clocks_ll;
/// Clock properties /// Clock properties
#[doc(hidden)]
pub trait Clock { pub trait Clock {
/// Frequency of the clock in [Hertz](fugit::HertzU32), using [fugit] types. /// Frequency of the clock in [Hertz](fugit::HertzU32), using [fugit] types.
fn frequency(&self) -> HertzU32; fn frequency(&self) -> HertzU32;
@ -82,37 +81,37 @@ pub trait Clock {
clippy::enum_variant_names, clippy::enum_variant_names,
reason = "MHz suffix indicates physical unit." reason = "MHz suffix indicates physical unit."
)] )]
/// FIXME: Remove Clock prefix once we can agree on a convention. #[non_exhaustive]
pub enum CpuClock { pub enum CpuClock {
/// 80MHz CPU clock /// 80MHz CPU clock
#[cfg(not(esp32h2))] #[cfg(not(esp32h2))]
Clock80MHz = 80, _80MHz = 80,
/// 96MHz CPU clock /// 96MHz CPU clock
#[cfg(esp32h2)] #[cfg(esp32h2)]
Clock96MHz = 96, _96MHz = 96,
/// 120MHz CPU clock /// 120MHz CPU clock
#[cfg(esp32c2)] #[cfg(esp32c2)]
Clock120MHz = 120, _120MHz = 120,
/// 160MHz CPU clock /// 160MHz CPU clock
#[cfg(not(any(esp32c2, esp32h2)))] #[cfg(not(any(esp32c2, esp32h2)))]
Clock160MHz = 160, _160MHz = 160,
/// 240MHz CPU clock /// 240MHz CPU clock
#[cfg(xtensa)] #[cfg(xtensa)]
Clock240MHz = 240, _240MHz = 240,
} }
impl Default for CpuClock { impl Default for CpuClock {
fn default() -> Self { fn default() -> Self {
cfg_if::cfg_if! { cfg_if::cfg_if! {
if #[cfg(esp32h2)] { if #[cfg(esp32h2)] {
Self::Clock96MHz Self::_96MHz
} else { } else {
// FIXME: I don't think this is correct in general? // FIXME: I don't think this is correct in general?
Self::Clock80MHz Self::_80MHz
} }
} }
} }
@ -123,13 +122,13 @@ impl CpuClock {
pub const fn max() -> Self { pub const fn max() -> Self {
cfg_if::cfg_if! { cfg_if::cfg_if! {
if #[cfg(esp32c2)] { if #[cfg(esp32c2)] {
Self::Clock120MHz Self::_120MHz
} else if #[cfg(any(esp32c3, esp32c6))] { } else if #[cfg(any(esp32c3, esp32c6))] {
Self::Clock160MHz Self::_160MHz
} else if #[cfg(esp32h2)] { } else if #[cfg(esp32h2)] {
Self::Clock96MHz Self::_96MHz
} else { } else {
Self::Clock240MHz Self::_240MHz
} }
} }
} }
@ -142,32 +141,33 @@ impl Clock for CpuClock {
} }
/// XTAL clock speed /// XTAL clock speed
#[instability::unstable]
#[derive(Debug, Clone, Copy)] #[derive(Debug, Clone, Copy)]
#[non_exhaustive] #[non_exhaustive]
pub enum XtalClock { pub enum XtalClock {
/// 26MHz XTAL clock /// 26MHz XTAL clock
#[cfg(any(esp32, esp32c2))] #[cfg(any(esp32, esp32c2))]
RtcXtalFreq26M, _26M,
/// 32MHz XTAL clock /// 32MHz XTAL clock
#[cfg(any(esp32c3, esp32h2, esp32s3))] #[cfg(any(esp32c3, esp32h2, esp32s3))]
RtcXtalFreq32M, _32M,
/// 40MHz XTAL clock /// 40MHz XTAL clock
#[cfg(not(esp32h2))] #[cfg(not(esp32h2))]
RtcXtalFreq40M, _40M,
/// Other XTAL clock /// Other XTAL clock
RtcXtalFreqOther(u32), Other(u32),
} }
impl Clock for XtalClock { impl Clock for XtalClock {
fn frequency(&self) -> HertzU32 { fn frequency(&self) -> HertzU32 {
match self { match self {
#[cfg(any(esp32, esp32c2))] #[cfg(any(esp32, esp32c2))]
XtalClock::RtcXtalFreq26M => HertzU32::MHz(26), XtalClock::_26M => HertzU32::MHz(26),
#[cfg(any(esp32c3, esp32h2, esp32s3))] #[cfg(any(esp32c3, esp32h2, esp32s3))]
XtalClock::RtcXtalFreq32M => HertzU32::MHz(32), XtalClock::_32M => HertzU32::MHz(32),
#[cfg(not(esp32h2))] #[cfg(not(esp32h2))]
XtalClock::RtcXtalFreq40M => HertzU32::MHz(40), XtalClock::_40M => HertzU32::MHz(40),
XtalClock::RtcXtalFreqOther(mhz) => HertzU32::MHz(*mhz), XtalClock::Other(mhz) => HertzU32::MHz(*mhz),
} }
} }
} }
@ -254,6 +254,7 @@ impl Clock for ApbClock {
#[derive(Debug, Clone, Copy)] #[derive(Debug, Clone, Copy)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive] #[non_exhaustive]
#[doc(hidden)]
pub struct Clocks { pub struct Clocks {
/// CPU clock frequency /// CPU clock frequency
pub cpu_clock: HertzU32, pub cpu_clock: HertzU32,
@ -315,7 +316,8 @@ impl Clocks {
/// ///
/// This function will run the frequency estimation if called before /// This function will run the frequency estimation if called before
/// [`crate::init()`]. /// [`crate::init()`].
pub fn xtal_freq() -> HertzU32 { #[cfg(systimer)]
pub(crate) fn xtal_freq() -> HertzU32 {
if let Some(clocks) = Self::try_get() { if let Some(clocks) = Self::try_get() {
clocks.xtal_clock clocks.xtal_clock
} else { } else {
@ -328,9 +330,9 @@ impl Clocks {
impl Clocks { impl Clocks {
fn measure_xtal_frequency() -> XtalClock { fn measure_xtal_frequency() -> XtalClock {
if RtcClock::estimate_xtal_frequency() > 33 { if RtcClock::estimate_xtal_frequency() > 33 {
XtalClock::RtcXtalFreq40M XtalClock::_40M
} else { } else {
XtalClock::RtcXtalFreq26M XtalClock::_26M
} }
} }
@ -340,9 +342,9 @@ impl Clocks {
if cpu_clock_speed != CpuClock::default() { if cpu_clock_speed != CpuClock::default() {
let pll_freq = match cpu_clock_speed { let pll_freq = match cpu_clock_speed {
CpuClock::Clock80MHz => PllClock::Pll320MHz, CpuClock::_80MHz => PllClock::Pll320MHz,
CpuClock::Clock160MHz => PllClock::Pll320MHz, CpuClock::_160MHz => PllClock::Pll320MHz,
CpuClock::Clock240MHz => PllClock::Pll480MHz, CpuClock::_240MHz => PllClock::Pll480MHz,
}; };
clocks_ll::esp32_rtc_update_to_xtal(xtal_freq, 1); clocks_ll::esp32_rtc_update_to_xtal(xtal_freq, 1);
@ -368,9 +370,9 @@ impl Clocks {
impl Clocks { impl Clocks {
fn measure_xtal_frequency() -> XtalClock { fn measure_xtal_frequency() -> XtalClock {
if RtcClock::estimate_xtal_frequency() > 33 { if RtcClock::estimate_xtal_frequency() > 33 {
XtalClock::RtcXtalFreq40M XtalClock::_40M
} else { } else {
XtalClock::RtcXtalFreq26M XtalClock::_26M
} }
} }
@ -408,7 +410,7 @@ impl Clocks {
#[cfg(esp32c3)] #[cfg(esp32c3)]
impl Clocks { impl Clocks {
fn measure_xtal_frequency() -> XtalClock { fn measure_xtal_frequency() -> XtalClock {
XtalClock::RtcXtalFreq40M XtalClock::_40M
} }
/// Configure the CPU clock speed. /// Configure the CPU clock speed.
@ -444,7 +446,7 @@ impl Clocks {
#[cfg(esp32c6)] #[cfg(esp32c6)]
impl Clocks { impl Clocks {
fn measure_xtal_frequency() -> XtalClock { fn measure_xtal_frequency() -> XtalClock {
XtalClock::RtcXtalFreq40M XtalClock::_40M
} }
/// Configure the CPU clock speed. /// Configure the CPU clock speed.
@ -481,7 +483,7 @@ impl Clocks {
#[cfg(esp32h2)] #[cfg(esp32h2)]
impl Clocks { impl Clocks {
fn measure_xtal_frequency() -> XtalClock { fn measure_xtal_frequency() -> XtalClock {
XtalClock::RtcXtalFreq32M XtalClock::_32M
} }
/// Configure the CPU clock speed. /// Configure the CPU clock speed.
@ -520,7 +522,7 @@ impl Clocks {
#[cfg(esp32s2)] #[cfg(esp32s2)]
impl Clocks { impl Clocks {
fn measure_xtal_frequency() -> XtalClock { fn measure_xtal_frequency() -> XtalClock {
XtalClock::RtcXtalFreq40M XtalClock::_40M
} }
/// Configure the CPU clock speed. /// Configure the CPU clock speed.
@ -542,7 +544,7 @@ impl Clocks {
#[cfg(esp32s3)] #[cfg(esp32s3)]
impl Clocks { impl Clocks {
fn measure_xtal_frequency() -> XtalClock { fn measure_xtal_frequency() -> XtalClock {
XtalClock::RtcXtalFreq40M XtalClock::_40M
} }
/// Configure the CPU clock speed. /// Configure the CPU clock speed.

8
esp-hal/src/rtc_cntl/mod.rs
View File

@ -563,12 +563,12 @@ impl RtcClock {
#[cfg(not(any(esp32c6, esp32h2)))] #[cfg(not(any(esp32c6, esp32h2)))]
pub fn xtal_freq() -> XtalClock { pub fn xtal_freq() -> XtalClock {
match Self::read_xtal_freq_mhz() { match Self::read_xtal_freq_mhz() {
None | Some(40) => XtalClock::RtcXtalFreq40M, None | Some(40) => XtalClock::_40M,
#[cfg(any(esp32c3, esp32s3))] #[cfg(any(esp32c3, esp32s3))]
Some(32) => XtalClock::RtcXtalFreq32M, Some(32) => XtalClock::_32M,
#[cfg(any(esp32, esp32c2))] #[cfg(any(esp32, esp32c2))]
Some(26) => XtalClock::RtcXtalFreq26M, Some(26) => XtalClock::_26M,
Some(other) => XtalClock::RtcXtalFreqOther(other), Some(other) => XtalClock::Other(other),
} }
} }

2
esp-hal/src/rtc_cntl/rtc/esp32c3.rs
View File

@ -86,7 +86,7 @@ pub(crate) fn init() {
} }
pub(crate) fn configure_clock() { pub(crate) fn configure_clock() {
assert!(matches!(RtcClock::xtal_freq(), XtalClock::RtcXtalFreq40M)); assert!(matches!(RtcClock::xtal_freq(), XtalClock::_40M));
unsafe { unsafe {
// from esp_clk_init: // from esp_clk_init:

6
esp-hal/src/rtc_cntl/rtc/esp32c6.rs
View File

@ -1200,7 +1200,7 @@ pub(crate) fn init() {
} }
pub(crate) fn configure_clock() { pub(crate) fn configure_clock() {
assert!(matches!(RtcClock::xtal_freq(), XtalClock::RtcXtalFreq40M)); assert!(matches!(RtcClock::xtal_freq(), XtalClock::_40M));
RtcClock::set_fast_freq(RtcFastClock::RtcFastClockRcFast); RtcClock::set_fast_freq(RtcFastClock::RtcFastClockRcFast);
@ -1429,8 +1429,8 @@ impl RtcClock {
/// bootloader, as passed to rtc_clk_init function. /// bootloader, as passed to rtc_clk_init function.
pub fn xtal_freq() -> XtalClock { pub fn xtal_freq() -> XtalClock {
match Self::xtal_freq_mhz() { match Self::xtal_freq_mhz() {
40 => XtalClock::RtcXtalFreq40M, 40 => XtalClock::_40M,
other => XtalClock::RtcXtalFreqOther(other), other => XtalClock::Other(other),
} }
} }

6
esp-hal/src/rtc_cntl/rtc/esp32h2.rs
View File

@ -120,7 +120,7 @@ pub(crate) fn init() {
} }
pub(crate) fn configure_clock() { pub(crate) fn configure_clock() {
assert!(matches!(RtcClock::xtal_freq(), XtalClock::RtcXtalFreq32M)); assert!(matches!(RtcClock::xtal_freq(), XtalClock::_32M));
RtcClock::set_fast_freq(RtcFastClock::RtcFastClockRcFast); RtcClock::set_fast_freq(RtcFastClock::RtcFastClockRcFast);
@ -269,8 +269,8 @@ impl RtcClock {
/// bootloader, as passed to rtc_clk_init function. /// bootloader, as passed to rtc_clk_init function.
pub fn xtal_freq() -> XtalClock { pub fn xtal_freq() -> XtalClock {
match Self::read_xtal_freq_mhz() { match Self::read_xtal_freq_mhz() {
None | Some(32) => XtalClock::RtcXtalFreq32M, None | Some(32) => XtalClock::_32M,
Some(other) => XtalClock::RtcXtalFreqOther(other), Some(other) => XtalClock::Other(other),
} }
} }

2
esp-hal/src/rtc_cntl/rtc/esp32s2.rs
View File

@ -9,7 +9,7 @@ use crate::{
pub(crate) fn init() {} pub(crate) fn init() {}
pub(crate) fn configure_clock() { pub(crate) fn configure_clock() {
assert!(matches!(RtcClock::xtal_freq(), XtalClock::RtcXtalFreq40M)); assert!(matches!(RtcClock::xtal_freq(), XtalClock::_40M));
RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m); RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m);

2
esp-hal/src/rtc_cntl/rtc/esp32s3.rs
View File

@ -9,7 +9,7 @@ use crate::{
pub(crate) fn init() {} pub(crate) fn init() {}
pub(crate) fn configure_clock() { pub(crate) fn configure_clock() {
assert!(matches!(RtcClock::xtal_freq(), XtalClock::RtcXtalFreq40M)); assert!(matches!(RtcClock::xtal_freq(), XtalClock::_40M));
RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m); RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m);