diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml index 47bd4f342..44ca95e53 100644 --- a/esp-hal/Cargo.toml +++ b/esp-hal/Cargo.toml @@ -52,14 +52,14 @@ xtensa-lx = { version = "0.9.0", optional = true } # IMPORTANT: # Each supported device MUST have its PAC included below along with a # corresponding feature. -esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } -esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } -esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } -esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } -esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } -esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } -esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } -esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true } +esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } +esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } +esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } +esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } +esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } +esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } +esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } +esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true } [target.'cfg(target_arch = "riscv32")'.dependencies] esp-riscv-rt = { version = "0.7.0", path = "../esp-riscv-rt" } diff --git a/esp-hal/src/aes/mod.rs b/esp-hal/src/aes/mod.rs index a861d8747..b6d3a4a29 100644 --- a/esp-hal/src/aes/mod.rs +++ b/esp-hal/src/aes/mod.rs @@ -520,7 +520,7 @@ pub mod dma { self.aes .aes .mode() - .modify(|_, w| w.mode().variant(mode as u8)); + .modify(|_, w| unsafe { w.mode().bits(mode as u8) }); } fn start_transform(&self) { diff --git a/esp-hal/src/assist_debug.rs b/esp-hal/src/assist_debug.rs index 39b797168..6ea71a3ca 100644 --- a/esp-hal/src/assist_debug.rs +++ b/esp-hal/src/assist_debug.rs @@ -68,11 +68,11 @@ impl<'d> DebugAssist<'d> { pub fn enable_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) { self.debug_assist .core_0_sp_min() - .write(|w| w.core_0_sp_min().variant(lower_bound)); + .write(|w| unsafe { w.core_0_sp_min().bits(lower_bound) }); self.debug_assist .core_0_sp_max() - .write(|w| w.core_0_sp_max().variant(upper_bound)); + .write(|w| unsafe { w.core_0_sp_max().bits(upper_bound) }); self.debug_assist.core_0_montr_ena().modify(|_, w| { w.core_0_sp_spill_min_ena() @@ -151,11 +151,11 @@ impl<'d> DebugAssist<'d> { pub fn enable_core1_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) { self.debug_assist .core_1_sp_min - .write(|w| w.core_1_sp_min().variant(lower_bound)); + .write(|w| w.core_1_sp_min().bits(lower_bound)); self.debug_assist .core_1_sp_max - .write(|w| w.core_1_sp_max().variant(upper_bound)); + .write(|w| w.core_1_sp_max().bits(upper_bound)); self.debug_assist.core_1_montr_ena.modify(|_, w| { w.core_1_sp_spill_min_ena() @@ -237,11 +237,11 @@ impl<'d> DebugAssist<'d> { ) { self.debug_assist .core_0_area_dram0_0_min() - .write(|w| w.core_0_area_dram0_0_min().variant(lower_bound)); + .write(|w| unsafe { w.core_0_area_dram0_0_min().bits(lower_bound) }); self.debug_assist .core_0_area_dram0_0_max() - .write(|w| w.core_0_area_dram0_0_max().variant(upper_bound)); + .write(|w| unsafe { w.core_0_area_dram0_0_max().bits(upper_bound) }); self.debug_assist.core_0_montr_ena().modify(|_, w| { w.core_0_area_dram0_0_rd_ena() @@ -314,11 +314,11 @@ impl<'d> DebugAssist<'d> { ) { self.debug_assist .core_0_area_dram0_1_min() - .write(|w| w.core_0_area_dram0_1_min().variant(lower_bound)); + .write(|w| unsafe { w.core_0_area_dram0_1_min().bits(lower_bound) }); self.debug_assist .core_0_area_dram0_1_max() - .write(|w| w.core_0_area_dram0_1_max().variant(upper_bound)); + .write(|w| unsafe { w.core_0_area_dram0_1_max().bits(upper_bound) }); self.debug_assist.core_0_montr_ena().modify(|_, w| { w.core_0_area_dram0_1_rd_ena() @@ -403,11 +403,11 @@ impl<'d> DebugAssist<'d> { ) { self.debug_assist .core_1_area_dram0_0_min() - .write(|w| w.core_1_area_dram0_0_min().variant(lower_bound)); + .write(|w| unsafe { w.core_1_area_dram0_0_min().bits(lower_bound) }); self.debug_assist .core_1_area_dram0_0_max() - .write(|w| w.core_1_area_dram0_0_max().variant(upper_bound)); + .write(|w| unsafe { w.core_1_area_dram0_0_max().bits(upper_bound) }); self.debug_assist.core_1_montr_ena().modify(|_, w| { w.core_1_area_dram0_0_rd_ena() @@ -480,11 +480,11 @@ impl<'d> DebugAssist<'d> { ) { self.debug_assist .core_1_area_dram0_1_min() - .write(|w| w.core_1_area_dram0_1_min().variant(lower_bound)); + .write(|w| unsafe { w.core_1_area_dram0_1_min().bits(lower_bound) }); self.debug_assist .core_1_area_dram0_1_max() - .write(|w| w.core_1_area_dram0_1_max().variant(upper_bound)); + .write(|w| unsafe { w.core_1_area_dram0_1_max().bits(upper_bound) }); self.debug_assist.core_1_montr_ena().modify(|_, w| { w.core_1_area_dram0_1_rd_ena() diff --git a/esp-hal/src/clock/clocks_ll/esp32.rs b/esp-hal/src/clock/clocks_ll/esp32.rs index fe3afc520..b97938b7a 100644 --- a/esp-hal/src/clock/clocks_ll/esp32.rs +++ b/esp-hal/src/clock/clocks_ll/esp32.rs @@ -60,7 +60,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock // Raise the voltage, if needed rtc_cntl .reg() - .modify(|_, w| w.dig_dbias_wak().variant(DIG_DBIAS_80M_160M as u8)); + .modify(|_, w| unsafe { w.dig_dbias_wak().bits(DIG_DBIAS_80M_160M as u8) }); // Configure 320M PLL match xtal_freq { @@ -98,7 +98,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock // Raise the voltage rtc_cntl .reg() - .modify(|_, w| w.dig_dbias_wak().variant(dig_dbias_240_m as u8)); + .modify(|_, w| unsafe { w.dig_dbias_wak().bits(dig_dbias_240_m as u8) }); // Configure 480M PLL match xtal_freq { @@ -176,6 +176,7 @@ pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) { unsafe { let value = (((freq.hz()) >> 12) & UINT16_MAX) | ((((freq.hz()) >> 12) & UINT16_MAX) << 16); esp32_update_cpu_freq(freq.hz()); + // set divider from XTAL to APB clock apb_cntl.sysclk_conf().modify(|_, w| { w.pre_div_cnt() @@ -183,9 +184,10 @@ pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) { }); // adjust ref_tick - apb_cntl.xtal_tick_conf().as_ptr().write_volatile( - ((freq.hz()) / REF_CLK_FREQ - 1) | apb_cntl.xtal_tick_conf().as_ptr().read_volatile(), - ); // TODO make it RW in SVD + apb_cntl.xtal_tick_conf().modify(|_, w| { + w.xtal_tick_num() + .bits(((freq.hz()) / REF_CLK_FREQ - 1) as u8) + }); // switch clock source rtc_cntl.clk_conf().modify(|_, w| w.soc_clk_sel().xtal()); @@ -194,7 +196,7 @@ pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) { // lower the voltage rtc_cntl .reg() - .modify(|_, w| w.dig_dbias_wak().variant(DIG_DBIAS_XTAL as u8)); + .modify(|_, w| w.dig_dbias_wak().bits(DIG_DBIAS_XTAL as u8)); } } @@ -236,7 +238,7 @@ pub(crate) fn set_cpu_freq(cpu_freq_mhz: crate::clock::CpuClock) { .write(|w| w.cpuperiod_sel().bits(per_conf as u8)); rtc_cntl .reg() - .modify(|_, w| w.dig_dbias_wak().variant(dbias as u8)); + .modify(|_, w| w.dig_dbias_wak().bits(dbias as u8)); rtc_cntl.clk_conf().modify(|_, w| w.soc_clk_sel().pll()); rtc_cntl.store5().modify(|_, w| w.scratch5().bits(value)); diff --git a/esp-hal/src/dma/gdma.rs b/esp-hal/src/dma/gdma.rs index 5edb48839..80e0caff3 100644 --- a/esp-hal/src/dma/gdma.rs +++ b/esp-hal/src/dma/gdma.rs @@ -99,7 +99,7 @@ impl RegisterAccess for Channel { fn set_out_priority(priority: DmaPriority) { Self::ch() .out_pri() - .write(|w| w.tx_pri().variant(priority as u8)); + .write(|w| unsafe { w.tx_pri().bits(priority as u8) }); } fn clear_out_interrupts() { @@ -145,7 +145,7 @@ impl RegisterAccess for Channel { fn set_out_peripheral(peripheral: u8) { Self::ch() .out_peri_sel() - .modify(|_, w| w.peri_out_sel().variant(peripheral)); + .modify(|_, w| unsafe { w.peri_out_sel().bits(peripheral) }); } fn start_out() { @@ -212,7 +212,7 @@ impl RegisterAccess for Channel { fn set_in_priority(priority: DmaPriority) { Self::ch() .in_pri() - .write(|w| w.rx_pri().variant(priority as u8)); + .write(|w| unsafe { w.rx_pri().bits(priority as u8) }); } fn clear_in_interrupts() { @@ -268,7 +268,7 @@ impl RegisterAccess for Channel { fn set_in_peripheral(peripheral: u8) { Self::ch() .in_peri_sel() - .modify(|_, w| w.peri_in_sel().variant(peripheral)); + .modify(|_, w| unsafe { w.peri_in_sel().bits(peripheral) }); } fn start_in() { diff --git a/esp-hal/src/dma/pdma.rs b/esp-hal/src/dma/pdma.rs index 7f166d218..859cb69ba 100644 --- a/esp-hal/src/dma/pdma.rs +++ b/esp-hal/src/dma/pdma.rs @@ -54,12 +54,12 @@ macro_rules! ImplSpiChannel { 2 => { dport .spi_dma_chan_sel() - .modify(|_, w| w.spi2_dma_chan_sel().variant(1)); + .modify(|_, w| unsafe { w.spi2_dma_chan_sel().bits(1) }); }, 3 => { dport .spi_dma_chan_sel() - .modify(|_, w| w.spi3_dma_chan_sel().variant(2)); + .modify(|_, w| unsafe { w.spi3_dma_chan_sel().bits(2) }); }, _ => panic!("Only SPI2 and SPI3 supported"), } diff --git a/esp-hal/src/gpio/etm.rs b/esp-hal/src/gpio/etm.rs index 853bab09b..3d5a3a520 100644 --- a/esp-hal/src/gpio/etm.rs +++ b/esp-hal/src/gpio/etm.rs @@ -315,7 +315,7 @@ fn enable_event_channel(channel: u8, pin: u8) { .modify(|_, w| w.etm_ch0_event_en().clear_bit()); gpio_sd .etm_event_ch_cfg(channel as usize) - .modify(|_, w| w.etm_ch0_event_sel().variant(pin)); + .modify(|_, w| unsafe { w.etm_ch0_event_sel().bits(pin) }); gpio_sd .etm_event_ch_cfg(channel as usize) .modify(|_, w| w.etm_ch0_event_en().set_bit()); diff --git a/esp-hal/src/gpio/lp_io.rs b/esp-hal/src/gpio/lp_io.rs index e8bd21029..4babee98e 100644 --- a/esp-hal/src/gpio/lp_io.rs +++ b/esp-hal/src/gpio/lp_io.rs @@ -38,11 +38,11 @@ impl LowPowerPin { if enable { lp_io .out_enable_w1ts() - .write(|w| w.enable_w1ts().variant(1 << PIN)); + .write(|w| unsafe { w.enable_w1ts().bits(1 << PIN) }); } else { lp_io .out_enable_w1tc() - .write(|w| w.enable_w1tc().variant(1 << PIN)); + .write(|w| unsafe { w.enable_w1tc().bits(1 << PIN) }); } } @@ -64,11 +64,11 @@ impl LowPowerPin { if level { lp_io .out_data_w1ts() - .write(|w| w.out_data_w1ts().variant(1 << PIN)); + .write(|w| unsafe { w.out_data_w1ts().bits(1 << PIN) }); } else { lp_io .out_data_w1tc() - .write(|w| w.out_data_w1tc().variant(1 << PIN)); + .write(|w| unsafe { w.out_data_w1tc().bits(1 << PIN) }); } } @@ -140,9 +140,9 @@ pub(crate) fn init_low_power_pin(pin: u8) { lp_aon .gpio_mux() - .modify(|r, w| w.sel().variant(r.sel().bits() | 1 << pin)); + .modify(|r, w| unsafe { w.sel().bits(r.sel().bits() | 1 << pin) }); - get_pin_reg(pin).modify(|_, w| w.mcu_sel().variant(0)); + get_pin_reg(pin).modify(|_, w| unsafe { w.mcu_sel().bits(0) }); } #[inline(always)] diff --git a/esp-hal/src/gpio/rtc_io.rs b/esp-hal/src/gpio/rtc_io.rs index 8c1f8fa3f..f81fdff93 100644 --- a/esp-hal/src/gpio/rtc_io.rs +++ b/esp-hal/src/gpio/rtc_io.rs @@ -40,21 +40,15 @@ impl LowPowerPin { #[doc(hidden)] pub fn output_enable(&self, enable: bool) { let rtc_io = unsafe { crate::peripherals::RTC_IO::steal() }; - if enable { - // TODO align PAC - #[cfg(esp32s2)] - rtc_io - .rtc_gpio_enable_w1ts() - .write(|w| w.reg_rtcio_reg_gpio_enable_w1ts().variant(1 << PIN)); - #[cfg(esp32s3)] + if enable { rtc_io .rtc_gpio_enable_w1ts() - .write(|w| w.rtc_gpio_enable_w1ts().variant(1 << PIN)); + .write(|w| unsafe { w.rtc_gpio_enable_w1ts().bits(1 << PIN) }); } else { rtc_io .enable_w1tc() - .write(|w| w.enable_w1tc().variant(1 << PIN)); + .write(|w| unsafe { w.enable_w1tc().bits(1 << PIN) }); } } @@ -74,27 +68,14 @@ impl LowPowerPin { pub fn set_level(&mut self, level: bool) { let rtc_io = unsafe { &*crate::peripherals::RTC_IO::PTR }; - // TODO align PACs - #[cfg(esp32s2)] if level { rtc_io .rtc_gpio_out_w1ts() - .write(|w| w.gpio_out_data_w1ts().variant(1 << PIN)); + .write(|w| unsafe { w.rtc_gpio_out_data_w1ts().bits(1 << PIN) }); } else { rtc_io .rtc_gpio_out_w1tc() - .write(|w| w.gpio_out_data_w1tc().variant(1 << PIN)); - } - - #[cfg(esp32s3)] - if level { - rtc_io - .rtc_gpio_out_w1ts() - .write(|w| w.rtc_gpio_out_data_w1ts().variant(1 << PIN)); - } else { - rtc_io - .rtc_gpio_out_w1tc() - .write(|w| w.rtc_gpio_out_data_w1tc().variant(1 << PIN)); + .write(|w| unsafe { w.rtc_gpio_out_data_w1tc().bits(1 << PIN) }); } } diff --git a/esp-hal/src/i2c.rs b/esp-hal/src/i2c.rs index 2fefe496b..c0eaa0dc4 100644 --- a/esp-hal/src/i2c.rs +++ b/esp-hal/src/i2c.rs @@ -1162,7 +1162,7 @@ pub trait Instance: crate::private::Sealed { .to() .write(|w| w.time_out_en().bit(time_out_en) .time_out_value() - .variant(time_out_value.try_into().unwrap()) + .bits(time_out_value.try_into().unwrap()) ); } } @@ -1538,7 +1538,7 @@ pub trait Instance: crate::private::Sealed { #[cfg(not(esp32))] fn reset_fifo(&self) { // First, reset the fifo buffers - self.register_block().fifo_conf().modify(|_, w| { + self.register_block().fifo_conf().modify(|_, w| unsafe { w.tx_fifo_rst() .set_bit() .rx_fifo_rst() @@ -1548,9 +1548,9 @@ pub trait Instance: crate::private::Sealed { .fifo_prt_en() .set_bit() .rxfifo_wm_thrhd() - .variant(1) + .bits(1) .txfifo_wm_thrhd() - .variant(8) + .bits(8) }); self.register_block() @@ -1571,7 +1571,7 @@ pub trait Instance: crate::private::Sealed { #[cfg(esp32)] fn reset_fifo(&self) { // First, reset the fifo buffers - self.register_block().fifo_conf().modify(|_, w| { + self.register_block().fifo_conf().modify(|_, w| unsafe { w.tx_fifo_rst() .set_bit() .rx_fifo_rst() @@ -1579,9 +1579,9 @@ pub trait Instance: crate::private::Sealed { .nonfifo_en() .clear_bit() .nonfifo_rx_thres() - .variant(1) + .bits(1) .nonfifo_tx_thres() - .variant(32) + .bits(32) }); self.register_block() @@ -1983,9 +1983,9 @@ pub mod lp_i2c { lp_aon .gpio_mux() .modify(|r, w| w.sel().bits(r.sel().bits() | (1 << 7))); - lp_io.gpio6().modify(|_, w| w.mcu_sel().variant(1)); // TODO + lp_io.gpio6().modify(|_, w| w.mcu_sel().bits(1)); // TODO - lp_io.gpio7().modify(|_, w| w.mcu_sel().variant(1)); + lp_io.gpio7().modify(|_, w| w.mcu_sel().bits(1)); // Set output mode to Normal lp_io.pin6().modify(|_, w| w.pad_driver().set_bit()); @@ -2169,7 +2169,7 @@ pub mod lp_i2c { w.time_out_en() .bit(time_out_en) .time_out_value() - .variant(time_out_value.try_into().unwrap()) + .bits(time_out_value.try_into().unwrap()) }); } diff --git a/esp-hal/src/i2s.rs b/esp-hal/src/i2s.rs index 3f0b1608c..6272d16d4 100644 --- a/esp-hal/src/i2s.rs +++ b/esp-hal/src/i2s.rs @@ -1172,25 +1172,25 @@ mod private { #[cfg(esp32)] i2s.clkm_conf().modify(|_, w| w.clka_ena().clear_bit()); - i2s.clkm_conf().modify(|_, w| { + i2s.clkm_conf().modify(|_, w| unsafe { w.clk_en() .set_bit() .clkm_div_num() - .variant(clock_settings.mclk_divider as u8) + .bits(clock_settings.mclk_divider as u8) }); - i2s.clkm_conf().modify(|_, w| { + i2s.clkm_conf().modify(|_, w| unsafe { w.clkm_div_a() - .variant(clock_settings.denominator as u8) + .bits(clock_settings.denominator as u8) .clkm_div_b() - .variant(clock_settings.numerator as u8) + .bits(clock_settings.numerator as u8) }); - i2s.sample_rate_conf().modify(|_, w| { + i2s.sample_rate_conf().modify(|_, w| unsafe { w.tx_bck_div_num() - .variant(clock_settings.bclk_divider as u8) + .bits(clock_settings.bclk_divider as u8) .rx_bck_div_num() - .variant(clock_settings.bclk_divider as u8) + .bits(clock_settings.bclk_divider as u8) }); } @@ -1203,9 +1203,9 @@ mod private { }; i2s.sample_rate_conf() - .modify(|_, w| w.tx_bits_mod().variant(data_format.channel_bits())); + .modify(|_, w| unsafe { w.tx_bits_mod().bits(data_format.channel_bits()) }); i2s.sample_rate_conf() - .modify(|_, w| w.rx_bits_mod().variant(data_format.channel_bits())); + .modify(|_, w| unsafe { w.rx_bits_mod().bits(data_format.channel_bits()) }); i2s.conf().modify(|_, w| { w.tx_slave_mod() @@ -1217,9 +1217,9 @@ mod private { .rx_msb_shift() .set_bit() // ? .tx_short_sync() - .variant(false) //?? + .bit(false) //?? .rx_short_sync() - .variant(false) //?? + .bit(false) //?? .tx_msb_right() .clear_bit() .rx_msb_right() @@ -1236,21 +1236,21 @@ mod private { .clear_bit() }); - i2s.fifo_conf().modify(|_, w| { + i2s.fifo_conf().modify(|_, w| unsafe { w.tx_fifo_mod() - .variant(fifo_mod) + .bits(fifo_mod) .tx_fifo_mod_force_en() .set_bit() .dscr_en() .set_bit() .rx_fifo_mod() - .variant(fifo_mod) + .bits(fifo_mod) .rx_fifo_mod_force_en() .set_bit() }); i2s.conf_chan() - .modify(|_, w| w.tx_chan_mod().variant(0).rx_chan_mod().variant(0)); // for now only stereo + .modify(|_, w| unsafe { w.tx_chan_mod().bits(0).rx_chan_mod().bits(0) }); // for now only stereo i2s.conf1() .modify(|_, w| w.tx_pcm_bypass().set_bit().rx_pcm_bypass().set_bit()); @@ -1338,12 +1338,12 @@ mod private { #[cfg(not(esp32))] i2s.rxeof_num() - .modify(|_, w| w.rx_eof_num().variant(len as u32)); + .modify(|_, w| unsafe { w.rx_eof_num().bits(len as u32) }); // On ESP32, the eof_num count in words. #[cfg(esp32)] i2s.rxeof_num() - .modify(|_, w| w.rx_eof_num().variant((len / 4) as u32)); + .modify(|_, w| unsafe { w.rx_eof_num().bits((len / 4) as u32) }); i2s.conf().modify(|_, w| w.rx_start().set_bit()); } @@ -1489,58 +1489,58 @@ mod private { clkm_div_yn1 = 0; } - i2s.tx_clkm_div_conf().modify(|_, w| { + i2s.tx_clkm_div_conf().modify(|_, w| unsafe { w.tx_clkm_div_x() - .variant(clkm_div_x as u16) + .bits(clkm_div_x as u16) .tx_clkm_div_y() - .variant(clkm_div_y as u16) + .bits(clkm_div_y as u16) .tx_clkm_div_yn1() - .variant(clkm_div_yn1 != 0) + .bit(clkm_div_yn1 != 0) .tx_clkm_div_z() - .variant(clkm_div_z as u16) + .bits(clkm_div_z as u16) }); - i2s.tx_clkm_conf().modify(|_, w| { + i2s.tx_clkm_conf().modify(|_, w| unsafe { w.clk_en() .set_bit() .tx_clk_active() .set_bit() .tx_clk_sel() - .variant(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz + .bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz .tx_clkm_div_num() - .variant(clock_settings.mclk_divider as u8) + .bits(clock_settings.mclk_divider as u8) }); - i2s.tx_conf1().modify(|_, w| { + i2s.tx_conf1().modify(|_, w| unsafe { w.tx_bck_div_num() - .variant((clock_settings.bclk_divider - 1) as u8) + .bits((clock_settings.bclk_divider - 1) as u8) }); - i2s.rx_clkm_div_conf().modify(|_, w| { + i2s.rx_clkm_div_conf().modify(|_, w| unsafe { w.rx_clkm_div_x() - .variant(clkm_div_x as u16) + .bits(clkm_div_x as u16) .rx_clkm_div_y() - .variant(clkm_div_y as u16) + .bits(clkm_div_y as u16) .rx_clkm_div_yn1() - .variant(clkm_div_yn1 != 0) + .bit(clkm_div_yn1 != 0) .rx_clkm_div_z() - .variant(clkm_div_z as u16) + .bits(clkm_div_z as u16) }); - i2s.rx_clkm_conf().modify(|_, w| { + i2s.rx_clkm_conf().modify(|_, w| unsafe { w.rx_clk_active() .set_bit() .rx_clk_sel() - .variant(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz + .bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz .rx_clkm_div_num() - .variant(clock_settings.mclk_divider as u8) + .bits(clock_settings.mclk_divider as u8) .mclk_sel() - .variant(true) + .bit(true) }); - i2s.rx_conf1().modify(|_, w| { + i2s.rx_conf1().modify(|_, w| unsafe { w.rx_bck_div_num() - .variant((clock_settings.bclk_divider - 1) as u8) + .bits((clock_settings.bclk_divider - 1) as u8) }); } @@ -1588,67 +1588,67 @@ mod private { clkm_div_yn1 = 0; } - pcr.i2s_tx_clkm_div_conf().modify(|_, w| { + pcr.i2s_tx_clkm_div_conf().modify(|_, w| unsafe { w.i2s_tx_clkm_div_x() - .variant(clkm_div_x as u16) + .bits(clkm_div_x as u16) .i2s_tx_clkm_div_y() - .variant(clkm_div_y as u16) + .bits(clkm_div_y as u16) .i2s_tx_clkm_div_yn1() - .variant(clkm_div_yn1 != 0) + .bit(clkm_div_yn1 != 0) .i2s_tx_clkm_div_z() - .variant(clkm_div_z as u16) + .bits(clkm_div_z as u16) }); - pcr.i2s_tx_clkm_conf().modify(|_, w| { + pcr.i2s_tx_clkm_conf().modify(|_, w| unsafe { w.i2s_tx_clkm_en() .set_bit() .i2s_tx_clkm_sel() - .variant(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz for C6 and 96MHz for H2 + .bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz for C6 and 96MHz for H2 .i2s_tx_clkm_div_num() - .variant(clock_settings.mclk_divider as u8) + .bits(clock_settings.mclk_divider as u8) }); #[cfg(not(esp32h2))] - i2s.tx_conf1().modify(|_, w| { + i2s.tx_conf1().modify(|_, w| unsafe { w.tx_bck_div_num() - .variant((clock_settings.bclk_divider - 1) as u8) + .bits((clock_settings.bclk_divider - 1) as u8) }); #[cfg(esp32h2)] - i2s.tx_conf().modify(|_, w| { + i2s.tx_conf().modify(|_, w| unsafe { w.tx_bck_div_num() - .variant((clock_settings.bclk_divider - 1) as u8) + .bits((clock_settings.bclk_divider - 1) as u8) }); - pcr.i2s_rx_clkm_div_conf().modify(|_, w| { + pcr.i2s_rx_clkm_div_conf().modify(|_, w| unsafe { w.i2s_rx_clkm_div_x() - .variant(clkm_div_x as u16) + .bits(clkm_div_x as u16) .i2s_rx_clkm_div_y() - .variant(clkm_div_y as u16) + .bits(clkm_div_y as u16) .i2s_rx_clkm_div_yn1() - .variant(clkm_div_yn1 != 0) + .bit(clkm_div_yn1 != 0) .i2s_rx_clkm_div_z() - .variant(clkm_div_z as u16) + .bits(clkm_div_z as u16) }); - pcr.i2s_rx_clkm_conf().modify(|_, w| { + pcr.i2s_rx_clkm_conf().modify(|_, w| unsafe { w.i2s_rx_clkm_en() .set_bit() .i2s_rx_clkm_sel() - .variant(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz for C6 and 96MHz for H2 + .bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz for C6 and 96MHz for H2 .i2s_rx_clkm_div_num() - .variant(clock_settings.mclk_divider as u8) + .bits(clock_settings.mclk_divider as u8) .i2s_mclk_sel() - .variant(true) + .bit(true) }); #[cfg(not(esp32h2))] - i2s.rx_conf1().modify(|_, w| { + i2s.rx_conf1().modify(|_, w| unsafe { w.rx_bck_div_num() - .variant((clock_settings.bclk_divider - 1) as u8) + .bits((clock_settings.bclk_divider - 1) as u8) }); #[cfg(esp32h2)] - i2s.rx_conf().modify(|_, w| { + i2s.rx_conf().modify(|_, w| unsafe { w.rx_bck_div_num() - .variant((clock_settings.bclk_divider - 1) as u8) + .bits((clock_settings.bclk_divider - 1) as u8) }); } @@ -1656,21 +1656,21 @@ mod private { let i2s = Self::register_block(); #[allow(clippy::useless_conversion)] - i2s.tx_conf1().modify(|_, w| { + i2s.tx_conf1().modify(|_, w| unsafe { w.tx_tdm_ws_width() - .variant((data_format.channel_bits() - 1).into()) + .bits((data_format.channel_bits() - 1).into()) .tx_bits_mod() - .variant(data_format.data_bits() - 1) + .bits(data_format.data_bits() - 1) .tx_tdm_chan_bits() - .variant(data_format.channel_bits() - 1) + .bits(data_format.channel_bits() - 1) .tx_half_sample_bits() - .variant(data_format.channel_bits() - 1) + .bits(data_format.channel_bits() - 1) }); #[cfg(not(esp32h2))] i2s.tx_conf1().modify(|_, w| w.tx_msb_shift().set_bit()); #[cfg(esp32h2)] i2s.tx_conf().modify(|_, w| w.tx_msb_shift().set_bit()); - i2s.tx_conf().modify(|_, w| { + i2s.tx_conf().modify(|_, w| unsafe { w.tx_mono() .clear_bit() .tx_mono_fst_vld() @@ -1690,12 +1690,12 @@ mod private { .tx_bit_order() .clear_bit() .tx_chan_mod() - .variant(0) + .bits(0) }); - i2s.tx_tdm_ctrl().modify(|_, w| { + i2s.tx_tdm_ctrl().modify(|_, w| unsafe { w.tx_tdm_tot_chan_num() - .variant(1) + .bits(1) .tx_tdm_chan0_en() .set_bit() .tx_tdm_chan1_en() @@ -1731,28 +1731,28 @@ mod private { }); #[allow(clippy::useless_conversion)] - i2s.rx_conf1().modify(|_, w| { + i2s.rx_conf1().modify(|_, w| unsafe { w.rx_tdm_ws_width() - .variant((data_format.channel_bits() - 1).into()) + .bits((data_format.channel_bits() - 1).into()) .rx_bits_mod() - .variant(data_format.data_bits() - 1) + .bits(data_format.data_bits() - 1) .rx_tdm_chan_bits() - .variant(data_format.channel_bits() - 1) + .bits(data_format.channel_bits() - 1) .rx_half_sample_bits() - .variant(data_format.channel_bits() - 1) + .bits(data_format.channel_bits() - 1) }); #[cfg(not(esp32h2))] i2s.rx_conf1().modify(|_, w| w.rx_msb_shift().set_bit()); #[cfg(esp32h2)] i2s.rx_conf().modify(|_, w| w.rx_msb_shift().set_bit()); - i2s.rx_conf().modify(|_, w| { + i2s.rx_conf().modify(|_, w| unsafe { w.rx_mono() .clear_bit() .rx_mono_fst_vld() .set_bit() .rx_stop_mode() - .variant(2) + .bits(2) .rx_tdm_en() .set_bit() .rx_pdm_en() @@ -1765,9 +1765,9 @@ mod private { .clear_bit() }); - i2s.rx_tdm_ctrl().modify(|_, w| { + i2s.rx_tdm_ctrl().modify(|_, w| unsafe { w.rx_tdm_tot_chan_num() - .variant(1) + .bits(1) .rx_tdm_pdm_chan0_en() .set_bit() .rx_tdm_pdm_chan1_en() @@ -1862,7 +1862,7 @@ mod private { fn rx_start(len: usize) { let i2s = Self::register_block(); i2s.rxeof_num() - .write(|w| w.rx_eof_num().variant(len as u16)); + .write(|w| unsafe { w.rx_eof_num().bits(len as u16) }); i2s.rx_conf().modify(|_, w| w.rx_start().set_bit()); } diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs index c7972ad38..895ddc543 100644 --- a/esp-hal/src/lcd_cam/lcd/i8080.rs +++ b/esp-hal/src/lcd_cam/lcd/i8080.rs @@ -103,23 +103,23 @@ where ], ); - lcd_cam.lcd_clock().write(|w| { + lcd_cam.lcd_clock().write(|w| unsafe { // Force enable the clock for all configuration registers. w.clk_en() .set_bit() .lcd_clk_sel() - .variant((i + 1) as _) + .bits((i + 1) as _) .lcd_clkm_div_num() - .variant(divider.div_num as _) + .bits(divider.div_num as _) .lcd_clkm_div_b() - .variant(divider.div_b as _) + .bits(divider.div_b as _) .lcd_clkm_div_a() - .variant(divider.div_a as _) + .bits(divider.div_a as _) // LCD_PCLK = LCD_CLK / 2 .lcd_clk_equ_sysclk() .clear_bit() .lcd_clkcnt_n() - .variant(2 - 1) // Must not be 0. + .bits(2 - 1) // Must not be 0. .lcd_ck_idle_edge() .bit(config.clock_mode.polarity == Polarity::IdleHigh) .lcd_ck_out_edge() @@ -143,18 +143,18 @@ where .lcd_2byte_en() .bit(is_2byte_mode) }); - lcd_cam.lcd_misc().write(|w| { + lcd_cam.lcd_misc().write(|w| unsafe { // Set the threshold for Async Tx FIFO full event. (5 bits) w.lcd_afifo_threshold_num() - .variant(0) + .bits(0) // Configure the setup cycles in LCD non-RGB mode. Setup cycles // expected = this value + 1. (6 bit) .lcd_vfk_cyclelen() - .variant(config.setup_cycles.saturating_sub(1) as _) + .bits(config.setup_cycles.saturating_sub(1) as _) // Configure the hold time cycles in LCD non-RGB mode. Hold // cycles expected = this value + 1. .lcd_vbk_cyclelen() - .variant(config.hold_cycles.saturating_sub(1) as _) + .bits(config.hold_cycles.saturating_sub(1) as _) // 1: Send the next frame data when the current frame is sent out. // 0: LCD stops when the current frame is sent out. .lcd_next_frame_en() @@ -180,40 +180,40 @@ where }); lcd_cam .lcd_dly_mode() - .write(|w| w.lcd_cd_mode().variant(config.cd_mode as u8)); - lcd_cam.lcd_data_dout_mode().write(|w| { + .write(|w| unsafe { w.lcd_cd_mode().bits(config.cd_mode as u8) }); + lcd_cam.lcd_data_dout_mode().write(|w| unsafe { w.dout0_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout1_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout2_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout3_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout4_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout5_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout6_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout7_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout8_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout9_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout10_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout11_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout12_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout13_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout14_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) .dout15_mode() - .variant(config.output_bit_mode as u8) + .bits(config.output_bit_mode as u8) }); lcd_cam.lcd_user().modify(|_, w| w.lcd_update().set_bit()); @@ -340,7 +340,7 @@ impl<'d, TX: Tx, P> I8080<'d, TX, P> { .modify(|_, w| w.lcd_cmd().set_bit().lcd_cmd_2_cycle_en().clear_bit()); self.lcd_cam .lcd_cmd_val() - .write(|w| w.lcd_cmd_value().variant(value.into() as _)); + .write(|w| unsafe { w.lcd_cmd_value().bits(value.into() as _) }); } Command::Two(first, second) => { self.lcd_cam @@ -349,19 +349,19 @@ impl<'d, TX: Tx, P> I8080<'d, TX, P> { let cmd = first.into() as u32 | (second.into() as u32) << 16; self.lcd_cam .lcd_cmd_val() - .write(|w| w.lcd_cmd_value().variant(cmd)); + .write(|w| unsafe { w.lcd_cmd_value().bits(cmd) }); } } // Set dummy length - self.lcd_cam.lcd_user().modify(|_, w| { + self.lcd_cam.lcd_user().modify(|_, w| unsafe { if dummy > 0 { // Enable DUMMY phase in LCD sequence when LCD starts. w.lcd_dummy() .set_bit() // Configure DUMMY cycles. DUMMY cycles = this value + 1. (2 bits) .lcd_dummy_cyclelen() - .variant((dummy - 1) as _) + .bits((dummy - 1) as _) } else { w.lcd_dummy().clear_bit() } @@ -401,13 +401,13 @@ impl<'d, TX: Tx, P> I8080<'d, TX, P> { .modify(|_, w| w.lcd_dout().clear_bit()); } else { // Set transfer length. - self.lcd_cam.lcd_user().modify(|_, w| { + self.lcd_cam.lcd_user().modify(|_, w| unsafe { if len <= 8192 { // Data length in fixed mode. (13 bits) w.lcd_always_out_en() .clear_bit() .lcd_dout_cyclelen() - .variant((len - 1) as _) + .bits((len - 1) as _) } else { // Enable continuous output. w.lcd_always_out_en().set_bit() diff --git a/esp-hal/src/mcpwm/mod.rs b/esp-hal/src/mcpwm/mod.rs index 2babc11c8..efcdea5c9 100644 --- a/esp-hal/src/mcpwm/mod.rs +++ b/esp-hal/src/mcpwm/mod.rs @@ -108,7 +108,7 @@ impl<'d, PWM: PwmPeripheral> MCPWM<'d, PWM> { // set prescaler peripheral .clk_cfg() - .write(|w| w.clk_prescale().variant(peripheral_clock.prescaler)); + .write(|w| unsafe { w.clk_prescale().bits(peripheral_clock.prescaler) }); // enable clock peripheral.clk().write(|w| w.en().set_bit()); @@ -120,7 +120,7 @@ impl<'d, PWM: PwmPeripheral> MCPWM<'d, PWM> { .pwm_clk_conf() .modify(|_, w| unsafe { w.pwm_div_num() - .variant(peripheral_clock.prescaler) + .bits(peripheral_clock.prescaler) .pwm_clkm_en() .set_bit() .pwm_clkm_sel() @@ -136,7 +136,7 @@ impl<'d, PWM: PwmPeripheral> MCPWM<'d, PWM> { .pwm_clk_conf() .modify(|_, w| unsafe { w.pwm_div_num() - .variant(peripheral_clock.prescaler) + .bits(peripheral_clock.prescaler) .pwm_clkm_en() .set_bit() .pwm_clkm_sel() diff --git a/esp-hal/src/mcpwm/operator.rs b/esp-hal/src/mcpwm/operator.rs index b2d7a510b..ec4917001 100644 --- a/esp-hal/src/mcpwm/operator.rs +++ b/esp-hal/src/mcpwm/operator.rs @@ -179,9 +179,9 @@ impl Operator { // We only write to our OPERATORx_TIMERSEL register let block = unsafe { &*PWM::block() }; block.operator_timersel().modify(|_, w| match OP { - 0 => w.operator0_timersel().variant(TIM), - 1 => w.operator1_timersel().variant(TIM), - 2 => w.operator2_timersel().variant(TIM), + 0 => unsafe { w.operator0_timersel().bits(TIM) }, + 1 => unsafe { w.operator1_timersel().bits(TIM) }, + 2 => unsafe { w.operator2_timersel().bits(TIM) }, _ => { unreachable!() } diff --git a/esp-hal/src/parl_io.rs b/esp-hal/src/parl_io.rs index 54aeeb5a5..22e5cf38b 100644 --- a/esp-hal/src/parl_io.rs +++ b/esp-hal/src/parl_io.rs @@ -351,12 +351,8 @@ where { fn configure(&mut self) { let pcr = unsafe { &*crate::peripherals::PCR::PTR }; - pcr.parl_clk_tx_conf().modify(|_, w| { - w.parl_clk_tx_sel() - .variant(3) - .parl_clk_tx_div_num() - .variant(0) - }); // PAD_CLK_TX, no divider + pcr.parl_clk_tx_conf() + .modify(|_, w| unsafe { w.parl_clk_tx_sel().bits(3).parl_clk_tx_div_num().bits(0) }); // PAD_CLK_TX, no divider self.pin .set_to_input() @@ -387,12 +383,8 @@ where { fn configure(&mut self) { let pcr = unsafe { &*crate::peripherals::PCR::PTR }; - pcr.parl_clk_rx_conf().modify(|_, w| { - w.parl_clk_rx_sel() - .variant(3) - .parl_clk_rx_div_num() - .variant(0) - }); // PAD_CLK_TX, no divider + pcr.parl_clk_rx_conf() + .modify(|_, w| unsafe { w.parl_clk_rx_sel().bits(3).parl_clk_rx_div_num().bits(0) }); // PAD_CLK_TX, no divider self.pin .set_to_input() @@ -1351,22 +1343,22 @@ where } let divider = divider as u16; - pcr.parl_clk_tx_conf().modify(|_, w| { + pcr.parl_clk_tx_conf().modify(|_, w| unsafe { w.parl_clk_tx_en() .set_bit() .parl_clk_tx_sel() - .variant(1) // PLL + .bits(1) // PLL .parl_clk_tx_div_num() - .variant(divider) + .bits(divider) }); - pcr.parl_clk_rx_conf().modify(|_, w| { + pcr.parl_clk_rx_conf().modify(|_, w| unsafe { w.parl_clk_rx_en() .set_bit() .parl_clk_rx_sel() - .variant(1) // PLL + .bits(1) // PLL .parl_clk_rx_div_num() - .variant(divider) + .bits(divider) }); Instance::set_rx_sw_en(true); Instance::set_rx_sample_mode(SampleMode::InternalSoftwareEnable); @@ -1806,7 +1798,7 @@ mod private { reg_block .tx_cfg0() - .modify(|_, w| w.tx_bus_wid_sel().variant(width as u8)); + .modify(|_, w| unsafe { w.tx_bus_wid_sel().bits(width as u8) }); } pub fn set_tx_idle_value(value: u16) { @@ -1814,7 +1806,7 @@ mod private { unsafe { crate::peripherals::PARL_IO::steal() }; reg_block .tx_cfg1() - .modify(|_, w| w.tx_idle_value().variant(value)); + .modify(|_, w| unsafe { w.tx_idle_value().bits(value) }); } pub fn set_tx_sample_edge(value: SampleEdge) { @@ -1822,7 +1814,7 @@ mod private { unsafe { crate::peripherals::PARL_IO::steal() }; reg_block .tx_cfg0() - .modify(|_, w| w.tx_smp_edge_sel().variant(value as u8 == 1)); + .modify(|_, w| w.tx_smp_edge_sel().bit(value as u8 == 1)); } pub fn set_tx_bit_order(value: BitPackOrder) { @@ -1830,7 +1822,7 @@ mod private { unsafe { crate::peripherals::PARL_IO::steal() }; reg_block .tx_cfg0() - .modify(|_, w| w.tx_bit_unpack_order().variant(value as u8 == 1)); + .modify(|_, w| w.tx_bit_unpack_order().bit(value as u8 == 1)); } pub fn clear_tx_interrupts() { @@ -1851,7 +1843,7 @@ mod private { reg_block .tx_cfg0() - .modify(|_, w| w.tx_bytelen().variant(len)); + .modify(|_, w| unsafe { w.tx_bytelen().bits(len) }); } pub fn is_tx_ready() -> bool { @@ -1894,7 +1886,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_bus_wid_sel().variant(width as u8)); + .modify(|_, w| unsafe { w.rx_bus_wid_sel().bits(width as u8) }); } pub fn rx_valid_pin_signal() -> crate::gpio::InputSignal { @@ -1923,7 +1915,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_data_bytelen().variant(len)); + .modify(|_, w| unsafe { w.rx_data_bytelen().bits(len) }); } pub fn set_rx_sample_mode(sample_mode: SampleMode) { @@ -1932,7 +1924,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_smp_mode_sel().variant(sample_mode as u8)); + .modify(|_, w| unsafe { w.rx_smp_mode_sel().bits(sample_mode as u8) }); } pub fn set_eof_gen_sel(mode: EofMode) { @@ -1941,7 +1933,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_eof_gen_sel().variant(mode == EofMode::EnableSignal)); + .modify(|_, w| w.rx_eof_gen_sel().bit(mode == EofMode::EnableSignal)); } pub fn set_rx_pulse_submode_sel(sel: u8) { @@ -1950,7 +1942,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_pulse_submode_sel().variant(sel)); + .modify(|_, w| unsafe { w.rx_pulse_submode_sel().bits(sel) }); } pub fn set_rx_level_submode_sel(sel: u8) { @@ -1959,7 +1951,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_level_submode_sel().variant(sel == 1)); + .modify(|_, w| w.rx_level_submode_sel().bit(sel == 1)); } pub fn set_rx_clk_edge_sel(edge: SampleEdge) { @@ -1968,7 +1960,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_clk_edge_sel().variant(edge as u8 == 1)); + .modify(|_, w| w.rx_clk_edge_sel().bit(edge as u8 == 1)); } pub fn set_rx_start(value: bool) { @@ -1992,17 +1984,17 @@ mod private { unsafe { crate::peripherals::PARL_IO::steal() }; reg_block .rx_cfg0() - .modify(|_, w| w.rx_bit_pack_order().variant(value as u8 == 1)); + .modify(|_, w| w.rx_bit_pack_order().bit(value as u8 == 1)); } pub fn set_rx_timeout_ticks(value: Option) { let reg_block: crate::peripherals::PARL_IO = unsafe { crate::peripherals::PARL_IO::steal() }; - reg_block.rx_cfg1().modify(|_, w| { + reg_block.rx_cfg1().modify(|_, w| unsafe { w.rx_timeout_en() .bit(value.is_some()) .rx_timeout_threshold() - .variant(value.unwrap_or(0xfff)) + .bits(value.unwrap_or(0xfff)) }); } @@ -2062,7 +2054,7 @@ mod private { reg_block .tx_data_cfg() - .modify(|_, w| w.tx_bus_wid_sel().variant(width as u8)); + .modify(|_, w| unsafe { w.tx_bus_wid_sel().bits(width as u8) }); } pub fn set_tx_idle_value(value: u16) { @@ -2070,7 +2062,7 @@ mod private { unsafe { crate::peripherals::PARL_IO::steal() }; reg_block .tx_genrl_cfg() - .modify(|_, w| w.tx_idle_value().variant(value)); + .modify(|_, w| unsafe { w.tx_idle_value().bits(value) }); } pub fn set_tx_sample_edge(value: SampleEdge) { @@ -2089,7 +2081,7 @@ mod private { unsafe { crate::peripherals::PARL_IO::steal() }; reg_block .tx_data_cfg() - .modify(|_, w| w.tx_data_order_inv().variant(value as u8 == 1)); + .modify(|_, w| w.tx_data_order_inv().bit(value as u8 == 1)); } pub fn clear_tx_interrupts() { @@ -2110,7 +2102,7 @@ mod private { reg_block .tx_data_cfg() - .modify(|_, w| w.tx_bitlen().variant((len as u32) * 8)); + .modify(|_, w| unsafe { w.tx_bitlen().bits((len as u32) * 8) }); } pub fn is_tx_ready() -> bool { @@ -2155,7 +2147,7 @@ mod private { reg_block .rx_data_cfg() - .modify(|_, w| w.rx_bus_wid_sel().variant(width as u8)); + .modify(|_, w| unsafe { w.rx_bus_wid_sel().bits(width as u8) }); } pub fn rx_valid_pin_signal() -> crate::gpio::InputSignal { @@ -2186,7 +2178,7 @@ mod private { reg_block .rx_data_cfg() - .modify(|_, w| w.rx_bitlen().variant((len as u32) * 8)); + .modify(|_, w| unsafe { w.rx_bitlen().bits((len as u32) * 8) }); } pub fn set_rx_sample_mode(sample_mode: SampleMode) { @@ -2195,7 +2187,7 @@ mod private { reg_block .rx_mode_cfg() - .modify(|_, w| w.rx_smp_mode_sel().variant(sample_mode as u8)); + .modify(|_, w| unsafe { w.rx_smp_mode_sel().bits(sample_mode as u8) }); } pub fn set_eof_gen_sel(mode: EofMode) { @@ -2204,7 +2196,7 @@ mod private { reg_block .rx_genrl_cfg() - .modify(|_, w| w.rx_eof_gen_sel().variant(mode == EofMode::EnableSignal)); + .modify(|_, w| w.rx_eof_gen_sel().bit(mode == EofMode::EnableSignal)); } pub fn set_rx_pulse_submode_sel(sel: u8) { @@ -2213,7 +2205,7 @@ mod private { reg_block .rx_mode_cfg() - .modify(|_, w| w.rx_pulse_submode_sel().variant(sel)); + .modify(|_, w| unsafe { w.rx_pulse_submode_sel().bits(sel) }); } pub fn set_rx_level_submode_sel(_sel: u8) { @@ -2255,17 +2247,17 @@ mod private { unsafe { crate::peripherals::PARL_IO::steal() }; reg_block .rx_data_cfg() - .modify(|_, w| w.rx_data_order_inv().variant(value as u8 == 1)); + .modify(|_, w| w.rx_data_order_inv().bit(value as u8 == 1)); } pub fn set_rx_timeout_ticks(value: Option) { let reg_block: crate::peripherals::PARL_IO = unsafe { crate::peripherals::PARL_IO::steal() }; - reg_block.rx_genrl_cfg().modify(|_, w| { + reg_block.rx_genrl_cfg().modify(|_, w| unsafe { w.rx_timeout_en() .bit(value.is_some()) .rx_timeout_thres() - .variant(value.unwrap_or(0xfff)) + .bits(value.unwrap_or(0xfff)) }); } diff --git a/esp-hal/src/rmt.rs b/esp-hal/src/rmt.rs index 543d03b64..294e1c95d 100644 --- a/esp-hal/src/rmt.rs +++ b/esp-hal/src/rmt.rs @@ -1,7 +1,7 @@ //! # Remote Control Peripheral (RMT) //! //! ## Overview -//! Some ESP32 variants include a remote control peripheral (RMT) that +//! Some ESP32 bitss include a remote control peripheral (RMT) that //! is designed to handle infrared remote control signals. For that //! purpose, it can convert bitstreams of data (from the RAM) into //! pulse codes and even modulate those codes into a carrier wave. @@ -1571,17 +1571,17 @@ mod chip_specific { #[cfg(not(pcr))] { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.sys_conf().modify(|_, w| { + rmt.sys_conf().modify(|_, w| unsafe { w.clk_en() .clear_bit() .sclk_sel() - .variant(crate::soc::constants::RMT_CLOCK_SRC) + .bits(crate::soc::constants::RMT_CLOCK_SRC) .sclk_div_num() - .variant(div as u8) + .bits(div as u8) .sclk_div_a() - .variant(0) + .bits(0) .sclk_div_b() - .variant(0) + .bits(0) .apb_fifo_mask() .set_bit() }); @@ -1590,17 +1590,22 @@ mod chip_specific { #[cfg(pcr)] { let pcr = unsafe { &*crate::peripherals::PCR::PTR }; - pcr.rmt_sclk_conf().modify(|_, w| { - w.sclk_sel() - .variant(crate::soc::constants::RMT_CLOCK_SRC) - .sclk_div_num() - .variant(div as u8) + pcr.rmt_sclk_conf().modify(|_, w| unsafe { + w.sclk_div_num() + .bits(div as u8) .sclk_div_a() - .variant(0) + .bits(0) .sclk_div_b() - .variant(0) + .bits(0) }); + #[cfg(esp32c6)] + pcr.rmt_sclk_conf() + .modify(|_, w| unsafe { w.sclk_sel().bits(crate::soc::constants::RMT_CLOCK_SRC) }); + #[cfg(not(esp32c6))] + pcr.rmt_sclk_conf() + .modify(|_, w| w.sclk_sel().bit(crate::soc::constants::RMT_CLOCK_SRC)); + let rmt = unsafe { &*crate::peripherals::RMT::PTR }; rmt.sys_conf().modify(|_, w| w.apb_fifo_mask().set_bit()); } @@ -1670,7 +1675,7 @@ mod chip_specific { fn set_divider(divider: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.ch_tx_conf0($ch_num).modify(|_, w| w.div_cnt().variant(divider)); + rmt.ch_tx_conf0($ch_num).modify(|_, w| unsafe { w.div_cnt().bits(divider) }); } fn update() { @@ -1681,22 +1686,22 @@ mod chip_specific { fn set_generate_repeat_interrupt(repeats: u16) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; if repeats > 1 { - rmt.ch_tx_lim($ch_num).modify(|_, w| { + rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe { w.loop_count_reset() .set_bit() .tx_loop_cnt_en() .set_bit() .tx_loop_num() - .variant(repeats) + .bits(repeats) }); } else { - rmt.ch_tx_lim($ch_num).modify(|_, w| { + rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe { w.loop_count_reset() .set_bit() .tx_loop_cnt_en() .clear_bit() .tx_loop_num() - .variant(0) + .bits(0) }); } @@ -1734,7 +1739,7 @@ mod chip_specific { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; rmt.chcarrier_duty($ch_num) - .write(|w| w.carrier_high().variant(high).carrier_low().variant(low)); + .write(|w| unsafe { w.carrier_high().bits(high).carrier_low().bits(low) }); rmt.ch_tx_conf0($ch_num).modify(|_, w| { w.carrier_en() @@ -1754,7 +1759,7 @@ mod chip_specific { fn set_memsize(memsize: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.ch_tx_conf0($ch_num).modify(|_, w| w.mem_size().variant(memsize)); + rmt.ch_tx_conf0($ch_num).modify(|_, w| unsafe { w.mem_size().bits(memsize) }); } fn start_tx() { @@ -1797,7 +1802,7 @@ mod chip_specific { fn set_threshold(threshold: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.ch_tx_lim($ch_num).modify(|_, w| w.tx_lim().variant(threshold as u16)); + rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe { w.tx_lim().bits(threshold as u16) }); } fn is_loopcount_interrupt_set() -> bool { @@ -1863,7 +1868,7 @@ mod chip_specific { fn set_divider(divider: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| w.div_cnt().variant(divider)); + rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| unsafe { w.div_cnt().bits(divider) }); } fn update() { @@ -1892,11 +1897,11 @@ mod chip_specific { fn set_carrier(carrier: bool, high: u16, low: u16, level: bool) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.ch_rx_carrier_rm($ch_index).write(|w| { + rmt.ch_rx_carrier_rm($ch_index).write(|w| unsafe { w.carrier_high_thres() - .variant(high) + .bits(high) .carrier_low_thres() - .variant(low) + .bits(low) }); rmt.[< ch $ch_num _rx_conf0 >]() @@ -1905,7 +1910,7 @@ mod chip_specific { fn set_memsize(memsize: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| w.mem_size().variant(memsize)); + rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| unsafe { w.mem_size().bits(memsize) }); } fn start_rx() { @@ -1940,18 +1945,18 @@ mod chip_specific { fn set_filter_threshold(value: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| { + rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| unsafe { w.rx_filter_en() .bit(value > 0) .rx_filter_thres() - .variant(value) + .bits(value) }); } fn set_idle_threshold(value: u16) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| w.idle_thres().variant(value)); + rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| unsafe { w.idle_thres().bits(value) }); } fn listen_interrupt(event: $crate::rmt::private::Event) { @@ -2079,7 +2084,7 @@ mod chip_specific { fn set_divider(divider: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num conf0 >]().modify(|_, w| w.div_cnt().variant(divider)); + rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.div_cnt().bits(divider) }); } fn update() { @@ -2090,9 +2095,9 @@ mod chip_specific { fn set_generate_repeat_interrupt(repeats: u16) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; if repeats > 1 { - rmt.ch_tx_lim($ch_num).modify(|_, w| w.tx_loop_num().variant(repeats)); + rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe { w.tx_loop_num().bits(repeats) }); } else { - rmt.ch_tx_lim($ch_num).modify(|_, w| w.tx_loop_num().variant(0)); + rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe { w.tx_loop_num().bits(0) }); } } @@ -2130,7 +2135,7 @@ mod chip_specific { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; rmt.chcarrier_duty($ch_num) - .write(|w| w.carrier_high().variant(high).carrier_low().variant(low)); + .write(|w| unsafe { w.carrier_high().bits(high).carrier_low().bits(low) }); rmt.[< ch $ch_num conf0 >]() .modify(|_, w| w.carrier_en().bit(carrier).carrier_out_lv().bit(level)); @@ -2145,7 +2150,7 @@ mod chip_specific { fn set_memsize(memsize: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num conf0 >]().modify(|_, w| w.mem_size().variant(memsize)); + rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.mem_size().bits(memsize) }); } fn start_tx() { @@ -2184,7 +2189,7 @@ mod chip_specific { fn set_threshold(threshold: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.ch_tx_lim($ch_num).modify(|_, w| w.tx_lim().variant(threshold as u16)); + rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe { w.tx_lim().bits(threshold as u16) }); } fn is_loopcount_interrupt_set() -> bool { @@ -2252,7 +2257,7 @@ mod chip_specific { fn set_divider(divider: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num conf0 >]().modify(|_, w| w.div_cnt().variant(divider)); + rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.div_cnt().bits(divider) }); } fn update() { @@ -2292,7 +2297,7 @@ mod chip_specific { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; rmt.chcarrier_duty($ch_num) - .write(|w| w.carrier_high().variant(high).carrier_low().variant(low)); + .write(|w| unsafe { w.carrier_high().bits(high).carrier_low().bits(low) }); rmt.[< ch $ch_num conf0 >]() .modify(|_, w| w.carrier_en().bit(carrier).carrier_out_lv().bit(level)); @@ -2301,7 +2306,7 @@ mod chip_specific { fn set_memsize(memsize: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num conf0 >]().modify(|_, w| w.mem_size().variant(memsize)); + rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.mem_size().bits(memsize) }); } fn start_rx() { @@ -2336,18 +2341,18 @@ mod chip_specific { fn set_filter_threshold(value: u8) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num conf1 >]().modify(|_, w| { + rmt.[< ch $ch_num conf1 >]().modify(|_, w| unsafe { w.rx_filter_en() .bit(value > 0) .rx_filter_thres() - .variant(value) + .bits(value) }); } fn set_idle_threshold(value: u16) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num conf0 >]().modify(|_, w| w.idle_thres().variant(value)); + rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.idle_thres().bits(value) }); } fn listen_interrupt(event: $crate::rmt::private::Event) { diff --git a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs index c749d7673..ba4e6cf2d 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs @@ -287,9 +287,9 @@ fn modem_clock_hal_select_wifi_lpclk_source(src: ModemClockLpclkSource) { | ModemClockLpclkSource::RcFast | ModemClockLpclkSource::MainXtal => w, - ModemClockLpclkSource::RC32K => w.clk_modem_32k_sel().variant(1), - ModemClockLpclkSource::XTAL32K => w.clk_modem_32k_sel().variant(0), - ModemClockLpclkSource::EXT32K => w.clk_modem_32k_sel().variant(2), + ModemClockLpclkSource::RC32K => w.clk_modem_32k_sel().bits(1), + ModemClockLpclkSource::XTAL32K => w.clk_modem_32k_sel().bits(0), + ModemClockLpclkSource::EXT32K => w.clk_modem_32k_sel().bits(2), }); } } @@ -1811,11 +1811,11 @@ impl RtcClock { let timg0 = unsafe { crate::peripherals::TIMG0::steal() }; while timg0.rtccalicfg().read().rtc_cali_rdy().bit_is_clear() {} - timg0.rtccalicfg().modify(|_, w| { + timg0.rtccalicfg().modify(|_, w| unsafe { w.rtc_cali_clk_sel() - .variant(0) // RTC_SLOW_CLK + .bits(0) // RTC_SLOW_CLK .rtc_cali_max() - .variant(100) + .bits(100) .rtc_cali_start_cycling() .clear_bit() .rtc_cali_start() diff --git a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs index 6b86c4de8..22f6989f2 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs @@ -618,11 +618,11 @@ impl RtcClock { let timg0 = unsafe { crate::peripherals::TIMG0::steal() }; while timg0.rtccalicfg().read().rtc_cali_rdy().bit_is_clear() {} - timg0.rtccalicfg().modify(|_, w| { + timg0.rtccalicfg().modify(|_, w| unsafe { w.rtc_cali_clk_sel() - .variant(0) // RTC_SLOW_CLK + .bits(0) // RTC_SLOW_CLK .rtc_cali_max() - .variant(100) + .bits(100) .rtc_cali_start_cycling() .clear_bit() .rtc_cali_start() diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs index 45d2ba2df..34ecb2c41 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs @@ -172,7 +172,7 @@ fn isolate_digital_gpio() { // make pad work as gpio (otherwise, deep_sleep bottom current will rise) io_mux .gpio(pin_num) - .modify(|_, w| w.mcu_sel().variant(RtcFunction::Digital as u8)); + .modify(|_, w| unsafe { w.mcu_sel().bits(RtcFunction::Digital as u8) }); } } } diff --git a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs index f5da82a36..beb4ecbda 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs @@ -197,8 +197,8 @@ impl<'a, 'b> RtcioWakeupSource<'a, 'b> { pin.rtc_set_config(true, true, RtcFunction::Rtc); - rtcio.pin(pin.number() as usize).modify(|_, w| { - w.wakeup_enable().set_bit().int_type().variant(match level { + rtcio.pin(pin.number() as usize).modify(|_, w| unsafe { + w.wakeup_enable().set_bit().int_type().bits(match level { WakeupLevel::Low => 4, WakeupLevel::High => 5, }) diff --git a/esp-hal/src/soc/esp32/psram.rs b/esp-hal/src/soc/esp32/psram.rs index a9f2c57c6..23462b660 100644 --- a/esp-hal/src/soc/esp32/psram.rs +++ b/esp-hal/src/soc/esp32/psram.rs @@ -655,7 +655,7 @@ pub(crate) mod utils { }); dport .pro_cache_ctrl1() - .modify(|_, w| w.pro_cmmu_sram_page_mode().variant(0)); + .modify(|_, w| w.pro_cmmu_sram_page_mode().bits(0)); // use Dram1 to visit ext sram. cache page mode : 1 -->16k 4 -->2k // 0-->32k,(accord with the settings in cache_sram_mmu_set) @@ -667,7 +667,7 @@ pub(crate) mod utils { }); dport .app_cache_ctrl1() - .modify(|_, w| w.app_cmmu_sram_page_mode().variant(0)); + .modify(|_, w| w.app_cmmu_sram_page_mode().bits(0)); } // ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) diff --git a/esp-hal/src/soc/esp32c2/radio_clocks.rs b/esp-hal/src/soc/esp32c2/radio_clocks.rs index 88b48f0e8..2d3c760e4 100644 --- a/esp-hal/src/soc/esp32c2/radio_clocks.rs +++ b/esp-hal/src/soc/esp32c2/radio_clocks.rs @@ -118,7 +118,7 @@ fn ble_rtc_clk_init() { // assume 40MHz xtal modem_clkrst .modem_lp_timer_conf() - .modify(|_, w| w.lp_timer_clk_div_num().variant(249)); + .modify(|_, w| unsafe { w.lp_timer_clk_div_num().bits(249) }); modem_clkrst .etm_clk_conf() diff --git a/esp-hal/src/soc/esp32c6/lp_core.rs b/esp-hal/src/soc/esp32c6/lp_core.rs index d460e329e..47360a16e 100644 --- a/esp-hal/src/soc/esp32c6/lp_core.rs +++ b/esp-hal/src/soc/esp32c6/lp_core.rs @@ -168,7 +168,7 @@ fn ulp_lp_core_run(wakeup_src: LpCoreWakeupSource) { LpCoreWakeupSource::HpCpu => 0x01, }; pmu.lp_cpu_pwr1() - .modify(|_, w| w.lp_cpu_wakeup_en().variant(src)); + .modify(|_, w| unsafe { w.lp_cpu_wakeup_en().bits(src) }); // Enable JTAG debugging lp_peri diff --git a/esp-hal/src/soc/esp32c6/radio_clocks.rs b/esp-hal/src/soc/esp32c6/radio_clocks.rs index 83364a6cf..eb2d48e06 100644 --- a/esp-hal/src/soc/esp32c6/radio_clocks.rs +++ b/esp-hal/src/soc/esp32c6/radio_clocks.rs @@ -336,11 +336,11 @@ fn init_clocks() { let pmu = &*esp32c6::PMU::PTR; pmu.hp_sleep_icg_modem() - .modify(|_, w| w.hp_sleep_dig_icg_modem_code().variant(0)); + .modify(|_, w| w.hp_sleep_dig_icg_modem_code().bits(0)); pmu.hp_modem_icg_modem() - .modify(|_, w| w.hp_modem_dig_icg_modem_code().variant(1)); + .modify(|_, w| w.hp_modem_dig_icg_modem_code().bits(1)); pmu.hp_active_icg_modem() - .modify(|_, w| w.hp_active_dig_icg_modem_code().variant(2)); + .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() .as_ptr() .write_volatile(pmu.imm_modem_icg().as_ptr().read_volatile() | 1 << 31); @@ -351,29 +351,29 @@ fn init_clocks() { let modem_syscon = &*esp32c6::MODEM_SYSCON::PTR; modem_syscon.clk_conf_power_st().modify(|_, w| { w.clk_modem_apb_st_map() - .variant(6) + .bits(6) .clk_modem_peri_st_map() - .variant(4) + .bits(4) .clk_wifi_st_map() - .variant(6) + .bits(6) .clk_bt_st_map() - .variant(6) + .bits(6) .clk_fe_st_map() - .variant(6) + .bits(6) .clk_zb_st_map() - .variant(6) + .bits(6) }); let modem_lpcon = &*esp32c6::MODEM_LPCON::PTR; modem_lpcon.clk_conf_power_st().modify(|_, w| { w.clk_lp_apb_st_map() - .variant(6) + .bits(6) .clk_i2c_mst_st_map() - .variant(6) + .bits(6) .clk_coex_st_map() - .variant(6) + .bits(6) .clk_wifipwr_st_map() - .variant(6) + .bits(6) }); modem_lpcon.wifi_lp_clk_conf().modify(|_, w| { @@ -389,7 +389,7 @@ fn init_clocks() { modem_lpcon .wifi_lp_clk_conf() - .modify(|_, w| w.clk_wifipwr_lp_div_num().variant(0)); + .modify(|_, w| w.clk_wifipwr_lp_div_num().bits(0)); modem_lpcon .clk_conf() diff --git a/esp-hal/src/soc/esp32h2/radio_clocks.rs b/esp-hal/src/soc/esp32h2/radio_clocks.rs index 4e19b9d74..5e7d14898 100644 --- a/esp-hal/src/soc/esp32h2/radio_clocks.rs +++ b/esp-hal/src/soc/esp32h2/radio_clocks.rs @@ -125,11 +125,11 @@ fn init_clocks() { let pmu = &*esp32h2::PMU::PTR; pmu.hp_sleep_icg_modem() - .modify(|_, w| w.hp_sleep_dig_icg_modem_code().variant(0)); + .modify(|_, w| w.hp_sleep_dig_icg_modem_code().bits(0)); pmu.hp_modem_icg_modem() - .modify(|_, w| w.hp_modem_dig_icg_modem_code().variant(1)); + .modify(|_, w| w.hp_modem_dig_icg_modem_code().bits(1)); pmu.hp_active_icg_modem() - .modify(|_, w| w.hp_active_dig_icg_modem_code().variant(2)); + .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() .as_ptr() .write_volatile(pmu.imm_modem_icg().as_ptr().read_volatile() | 1 << 31); diff --git a/esp-hal/src/soc/esp32s3/psram.rs b/esp-hal/src/soc/esp32s3/psram.rs index 5587d7392..f0643ac94 100644 --- a/esp-hal/src/soc/esp32s3/psram.rs +++ b/esp-hal/src/soc/esp32s3/psram.rs @@ -731,7 +731,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(cs1_io as usize) - .modify(|_, w| w.mcu_sel().variant(FUNC_SPICS1_SPICS1)) + .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1)) } } else { unsafe { @@ -740,7 +740,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(cs1_io as usize) - .modify(|_, w| w.mcu_sel().variant(PIN_FUNC_GPIO)) + .modify(|_, w| w.mcu_sel().bits(PIN_FUNC_GPIO)) } } @@ -1375,7 +1375,7 @@ pub(crate) mod utils { for pin in pins { unsafe { let iomux = &*esp32s3::IO_MUX::PTR; - iomux.gpio(*pin).modify(|_, w| w.fun_drv().variant(3)) + iomux.gpio(*pin).modify(|_, w| w.fun_drv().bits(3)) } } } @@ -1474,7 +1474,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(OCT_PSRAM_CS1_IO as usize) - .modify(|_, w| w.mcu_sel().variant(FUNC_SPICS1_SPICS1)) + .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1)) } // Set mspi cs1 drive strength @@ -1482,7 +1482,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(OCT_PSRAM_CS1_IO as usize) - .modify(|_, w| w.fun_drv().variant(3)) + .modify(|_, w| w.fun_drv().bits(3)) } // Set psram clock pin drive strength diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs index 891a4e656..1ceb42bca 100644 --- a/esp-hal/src/spi/master.rs +++ b/esp-hal/src/spi/master.rs @@ -1218,22 +1218,24 @@ pub mod dma { // set cmd, address, dummy cycles let reg_block = self.spi.register_block(); if !cmd.is_none() { - reg_block.user2().modify(|_, w| { + reg_block.user2().modify(|_, w| unsafe { w.usr_command_bitlen() - .variant((cmd.width() - 1) as u8) + .bits((cmd.width() - 1) as u8) .usr_command_value() - .variant(cmd.value()) + .bits(cmd.value()) }); } #[cfg(not(esp32))] if !address.is_none() { - reg_block - .user1() - .modify(|_, w| w.usr_addr_bitlen().variant((address.width() - 1) as u8)); + reg_block.user1().modify(|_, w| unsafe { + w.usr_addr_bitlen().bits((address.width() - 1) as u8) + }); let addr = address.value() << (32 - address.width()); - reg_block.addr().write(|w| w.usr_addr_value().variant(addr)); + reg_block + .addr() + .write(|w| unsafe { w.usr_addr_value().bits(addr) }); } #[cfg(esp32)] @@ -1249,7 +1251,7 @@ pub mod dma { if dummy > 0 { reg_block .user1() - .modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1)); + .modify(|_, w| unsafe { w.usr_dummy_cyclelen().bits(dummy - 1) }); } self.spi @@ -1289,22 +1291,24 @@ pub mod dma { // set cmd, address, dummy cycles let reg_block = self.spi.register_block(); if !cmd.is_none() { - reg_block.user2().modify(|_, w| { + reg_block.user2().modify(|_, w| unsafe { w.usr_command_bitlen() - .variant((cmd.width() - 1) as u8) + .bits((cmd.width() - 1) as u8) .usr_command_value() - .variant(cmd.value()) + .bits(cmd.value()) }); } #[cfg(not(esp32))] if !address.is_none() { - reg_block - .user1() - .modify(|_, w| w.usr_addr_bitlen().variant((address.width() - 1) as u8)); + reg_block.user1().modify(|_, w| unsafe { + w.usr_addr_bitlen().bits((address.width() - 1) as u8) + }); let addr = address.value() << (32 - address.width()); - reg_block.addr().write(|w| w.usr_addr_value().variant(addr)); + reg_block + .addr() + .write(|w| unsafe { w.usr_addr_value().bits(addr) }); } #[cfg(esp32)] @@ -1320,7 +1324,7 @@ pub mod dma { if dummy > 0 { reg_block .user1() - .modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1)); + .modify(|_, w| unsafe { w.usr_dummy_cyclelen().bits(dummy - 1) }); } self.spi @@ -2857,11 +2861,11 @@ pub trait Instance: crate::private::Sealed { // set cmd, address, dummy cycles let reg_block = self.register_block(); if !cmd.is_none() { - reg_block.user2().modify(|_, w| { + reg_block.user2().modify(|_, w| unsafe { w.usr_command_bitlen() - .variant((cmd.width() - 1) as u8) + .bits((cmd.width() - 1) as u8) .usr_command_value() - .variant(cmd.value()) + .bits(cmd.value()) }); } @@ -2869,10 +2873,12 @@ pub trait Instance: crate::private::Sealed { if !address.is_none() { reg_block .user1() - .modify(|_, w| w.usr_addr_bitlen().variant((address.width() - 1) as u8)); + .modify(|_, w| unsafe { w.usr_addr_bitlen().bits((address.width() - 1) as u8) }); let addr = address.value() << (32 - address.width()); - reg_block.addr().write(|w| w.usr_addr_value().variant(addr)); + reg_block + .addr() + .write(|w| unsafe { w.usr_addr_value().bits(addr) }); } #[cfg(esp32)] @@ -2888,7 +2894,7 @@ pub trait Instance: crate::private::Sealed { if dummy > 0 { reg_block .user1() - .modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1)); + .modify(|_, w| unsafe { w.usr_dummy_cyclelen().bits(dummy - 1) }); } if !buffer.is_empty() { @@ -2920,11 +2926,11 @@ pub trait Instance: crate::private::Sealed { // set cmd, address, dummy cycles let reg_block = self.register_block(); if !cmd.is_none() { - reg_block.user2().modify(|_, w| { + reg_block.user2().modify(|_, w| unsafe { w.usr_command_bitlen() - .variant((cmd.width() - 1) as u8) + .bits((cmd.width() - 1) as u8) .usr_command_value() - .variant(cmd.value()) + .bits(cmd.value()) }); } @@ -2932,10 +2938,12 @@ pub trait Instance: crate::private::Sealed { if !address.is_none() { reg_block .user1() - .modify(|_, w| w.usr_addr_bitlen().variant((address.width() - 1) as u8)); + .modify(|_, w| unsafe { w.usr_addr_bitlen().bits((address.width() - 1) as u8) }); let addr = address.value() << (32 - address.width()); - reg_block.addr().write(|w| w.usr_addr_value().variant(addr)); + reg_block + .addr() + .write(|w| unsafe { w.usr_addr_value().bits(addr) }); } #[cfg(esp32)] @@ -2951,7 +2959,7 @@ pub trait Instance: crate::private::Sealed { if dummy > 0 { reg_block .user1() - .modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1)); + .modify(|_, w| unsafe { w.usr_dummy_cyclelen().bits(dummy - 1) }); } self.configure_datalen(buffer.len() as u32 * 8); diff --git a/esp-hal/src/trace.rs b/esp-hal/src/trace.rs index a8f8f349c..076e8e747 100644 --- a/esp-hal/src/trace.rs +++ b/esp-hal/src/trace.rs @@ -76,13 +76,12 @@ where pub fn start_trace(&mut self, buffer: &'d mut [u8]) { let reg_block = self.peripheral.register_block(); - reg_block.mem_start_addr().modify(|_, w| { - w.mem_start_addr() - .variant(buffer.as_ptr() as *const _ as u32) - }); - reg_block.mem_end_addr().modify(|_, w| { + reg_block + .mem_start_addr() + .modify(|_, w| unsafe { w.mem_start_addr().bits(buffer.as_ptr() as *const _ as u32) }); + reg_block.mem_end_addr().modify(|_, w| unsafe { w.mem_end_addr() - .variant((buffer.as_ptr() as *const _ as u32) + (buffer.len() as u32)) + .bits((buffer.as_ptr() as *const _ as u32) + (buffer.len() as u32)) }); reg_block .mem_addr_update() diff --git a/esp-hal/src/twai/mod.rs b/esp-hal/src/twai/mod.rs index 0cb7f2e40..0177fd494 100644 --- a/esp-hal/src/twai/mod.rs +++ b/esp-hal/src/twai/mod.rs @@ -697,19 +697,16 @@ where let prescale = prescale as u8; // Set up the prescaler and sync jump width. - T::register_block().bus_timing_0().modify(|_, w| { - w.baud_presc() - .variant(prescale) - .sync_jump_width() - .variant(sjw) - }); + T::register_block() + .bus_timing_0() + .modify(|_, w| unsafe { w.baud_presc().bits(prescale).sync_jump_width().bits(sjw) }); // Set up the time segment 1, time segment 2, and triple sample. - T::register_block().bus_timing_1().modify(|_, w| { + T::register_block().bus_timing_1().modify(|_, w| unsafe { w.time_seg1() - .variant(tseg_1) + .bits(tseg_1) .time_seg2() - .variant(tseg_2) + .bits(tseg_2) .time_samp() .bit(triple_sample) }); @@ -749,7 +746,7 @@ where pub fn set_error_warning_limit(&mut self, limit: u8) { T::register_block() .err_warning_limit() - .write(|w| w.err_warning_limit().variant(limit)); + .write(|w| unsafe { w.err_warning_limit().bits(limit) }); } /// Put the peripheral into Operation Mode, allowing the transmission and @@ -1140,7 +1137,7 @@ pub trait OperationInstance: Instance { register_block .data_0() - .write(|w| w.tx_byte_0().variant(data_0)); + .write(|w| unsafe { w.tx_byte_0().bits(data_0) }); // Assemble the identifier information of the packet. match frame.id { @@ -1149,27 +1146,27 @@ pub trait OperationInstance: Instance { register_block .data_1() - .write(|w| w.tx_byte_1().variant((id >> 3) as u8)); + .write(|w| unsafe { w.tx_byte_1().bits((id >> 3) as u8) }); register_block .data_2() - .write(|w| w.tx_byte_2().variant((id << 5) as u8)); + .write(|w| unsafe { w.tx_byte_2().bits((id << 5) as u8) }); } Id::Extended(id) => { let id = id.as_raw(); register_block .data_1() - .write(|w| w.tx_byte_1().variant((id >> 21) as u8)); + .write(|w| unsafe { w.tx_byte_1().bits((id >> 21) as u8) }); register_block .data_2() - .write(|w| w.tx_byte_2().variant((id >> 13) as u8)); + .write(|w| unsafe { w.tx_byte_2().bits((id >> 13) as u8) }); register_block .data_3() - .write(|w| w.tx_byte_3().variant((id >> 5) as u8)); + .write(|w| unsafe { w.tx_byte_3().bits((id >> 5) as u8) }); register_block .data_4() - .write(|w| w.tx_byte_4().variant((id << 3) as u8)); + .write(|w| unsafe { w.tx_byte_4().bits((id << 3) as u8) }); } } diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index e21177b07..f5d3f8b09 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -2034,13 +2034,13 @@ pub mod lp_uart { lp_aon .gpio_mux() - .modify(|r, w| w.sel().variant(r.sel().bits() | 1 << 4)); + .modify(|r, w| unsafe { w.sel().bits(r.sel().bits() | 1 << 4) }); lp_aon .gpio_mux() - .modify(|r, w| w.sel().variant(r.sel().bits() | 1 << 5)); + .modify(|r, w| unsafe { w.sel().bits(r.sel().bits() | 1 << 5) }); - lp_io.gpio4().modify(|_, w| w.mcu_sel().variant(1)); - lp_io.gpio5().modify(|_, w| w.mcu_sel().variant(1)); + lp_io.gpio4().modify(|_, w| unsafe { w.mcu_sel().bits(1) }); + lp_io.gpio5().modify(|_, w| unsafe { w.mcu_sel().bits(1) }); Self::new_with_config(uart, Config::default()) }