Avoid moving inside SpiDmaBus, abort dropped transfers (#2216)
* Drop State from DMA * Simplify Error paths * Cancel dropped transfers, fix and test * Fix C6 * Avoid cancelling a completed transaction * Do not implement DmaTxRxBuf for references * Remove unnecessary import * Merge BufferRef structs * Move wait impl to the peripheral * Allow the current byte to complete * Restore SpiDmaTransfer::is_done * Explain cancel code * Fix test formatting * Changelog * Simplify implementation * Make sure everything gets dropped * Remove unnecessary PhantomData * Remove OptionalFuture * Adjust test to a more realistic clock frequency
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@ -62,6 +62,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- `EspTwaiFrame` constructors now accept any type that converts into `esp_hal::twai::Id` (#2207)
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- `EspTwaiFrame` constructors now accept any type that converts into `esp_hal::twai::Id` (#2207)
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- Change `DmaTxBuf` to support PSRAM on `esp32s3` (#2161)
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- Change `DmaTxBuf` to support PSRAM on `esp32s3` (#2161)
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- I2c `transaction` is now also available as a inherent function, lift size limit on `write`,`read` and `write_read` (#2262)
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- I2c `transaction` is now also available as a inherent function, lift size limit on `write`,`read` and `write_read` (#2262)
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- SPI transactions are now cancelled if the transfer object (or async Future) is dropped. (#2216)
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### Fixed
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### Fixed
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File diff suppressed because it is too large
Load Diff
@ -12,7 +12,7 @@ use embedded_hal::spi::SpiBus;
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#[cfg(pcnt)]
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#[cfg(pcnt)]
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use embedded_hal_async::spi::SpiBus as SpiBusAsync;
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use embedded_hal_async::spi::SpiBus as SpiBusAsync;
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use esp_hal::{
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use esp_hal::{
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dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
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dma::{Dma, DmaDescriptor, DmaPriority, DmaRxBuf, DmaTxBuf},
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dma_buffers,
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dma_buffers,
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gpio::{Io, Level, NoPin},
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gpio::{Io, Level, NoPin},
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peripherals::SPI2,
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peripherals::SPI2,
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@ -37,6 +37,11 @@ cfg_if::cfg_if! {
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struct Context {
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struct Context {
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spi: Spi<'static, SPI2, FullDuplexMode>,
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spi: Spi<'static, SPI2, FullDuplexMode>,
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dma_channel: DmaChannelCreator,
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dma_channel: DmaChannelCreator,
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// Reuse the really large buffer so we don't run out of DRAM with many tests
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rx_buffer: &'static mut [u8],
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rx_descriptors: &'static mut [DmaDescriptor],
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tx_buffer: &'static mut [u8],
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tx_descriptors: &'static mut [DmaDescriptor],
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#[cfg(pcnt)]
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#[cfg(pcnt)]
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pcnt_source: InputSignal,
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pcnt_source: InputSignal,
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#[cfg(pcnt)]
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#[cfg(pcnt)]
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@ -74,17 +79,21 @@ mod tests {
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.with_mosi(mosi)
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.with_mosi(mosi)
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.with_miso(mosi_loopback);
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.with_miso(mosi_loopback);
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cfg_if::cfg_if! {
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
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if #[cfg(pcnt)] {
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let pcnt = Pcnt::new(peripherals.PCNT);
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#[cfg(pcnt)]
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Context {
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let pcnt = Pcnt::new(peripherals.PCNT);
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spi, dma_channel,
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Context {
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pcnt_source: mosi_loopback_pcnt,
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spi,
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pcnt_unit: pcnt.unit0,
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dma_channel,
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}
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rx_buffer,
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} else {
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rx_descriptors,
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Context { spi, dma_channel }
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tx_buffer,
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}
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tx_descriptors,
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#[cfg(pcnt)]
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pcnt_source: mosi_loopback_pcnt,
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#[cfg(pcnt)]
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pcnt_unit: pcnt.unit0,
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}
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}
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}
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}
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@ -251,9 +260,8 @@ mod tests {
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fn test_symmetric_dma_transfer(ctx: Context) {
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fn test_symmetric_dma_transfer(ctx: Context) {
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// This test case sends a large amount of data, multiple times to verify that
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// This test case sends a large amount of data, multiple times to verify that
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// https://github.com/esp-rs/esp-hal/issues/2151 is and remains fixed.
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// https://github.com/esp-rs/esp-hal/issues/2151 is and remains fixed.
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
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let mut dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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for (i, v) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
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for (i, v) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
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*v = (i % 255) as u8;
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*v = (i % 255) as u8;
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@ -478,4 +486,91 @@ mod tests {
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assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
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assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
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}
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}
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#[test]
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#[timeout(2)]
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fn cancel_stops_transaction(mut ctx: Context) {
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// Slow down. At 80kHz, the transfer is supposed to take a bit over 3 seconds.
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// This means that without working cancellation, the test case should
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// fail.
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ctx.spi.change_bus_frequency(80.kHz());
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// Set up a large buffer that would trigger a timeout
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let dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
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let spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
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let mut transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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transfer.cancel();
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transfer.wait();
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}
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#[test]
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#[timeout(3)]
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fn can_transmit_after_cancel(mut ctx: Context) {
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// Slow down. At 80kHz, the transfer is supposed to take a bit over 3 seconds.
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ctx.spi.change_bus_frequency(80.kHz());
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// Set up a large buffer that would trigger a timeout
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let mut dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
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let mut spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
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let mut transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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transfer.cancel();
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(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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spi.change_bus_frequency(10000.kHz());
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let transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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if dma_tx_buf.as_slice() != dma_rx_buf.as_slice() {
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defmt::info!("dma_tx_buf: {:?}", dma_tx_buf.as_slice()[0..100]);
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defmt::info!("dma_rx_buf: {:?}", dma_rx_buf.as_slice()[0..100]);
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panic!("Failed to transmit after cancel");
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}
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}
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#[test]
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#[timeout(3)]
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async fn cancelling_an_awaited_transfer_does_nothing(ctx: Context) {
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// Set up a large buffer that would trigger a timeout
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let dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
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let spi = ctx.spi.with_dma(
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ctx.dma_channel
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.configure_for_async(false, DmaPriority::Priority0),
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);
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let mut transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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transfer.wait_for_done().await;
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transfer.cancel();
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transfer.wait_for_done().await;
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transfer.cancel();
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_ = transfer.wait();
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}
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}
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}
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