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Change code for clarity

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This commit is contained in:
Björn Quentin 2025-01-03 15:53:56 +01:00
parent ce6d82525e
commit 3994dc6de3
1 changed files with 3 additions and 3 deletions
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6
esp-hal/src/soc/esp32s3/psram.rs
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@ -174,11 +174,11 @@ pub(crate) fn init_psram(config: PsramConfig) {
let mut mapped_pages = 0; let mut mapped_pages = 0;
for i in (0..FLASH_MMU_TABLE_SIZE).rev() { for i in (0..FLASH_MMU_TABLE_SIZE).rev() {
if mmu_table_ptr.add(i).read_volatile() != MMU_INVALID { if mmu_table_ptr.add(i).read_volatile() != MMU_INVALID {
mapped_pages = i; mapped_pages = (i + 1) as u32;
break; break;
} }
} }
let start = EXTMEM_ORIGIN + MMU_PAGE_SIZE * (mapped_pages + 1) as u32; let start = EXTMEM_ORIGIN + (MMU_PAGE_SIZE * mapped_pages);
debug!("PSRAM start address = {:x}", start); debug!("PSRAM start address = {:x}", start);
// Configure the mode of instruction cache : cache size, cache line size. // Configure the mode of instruction cache : cache size, cache line size.
@ -188,7 +188,7 @@ pub(crate) fn init_psram(config: PsramConfig) {
CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE, CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE,
); );
// If we need use SPIRAM, we should use data cache.Connfigure the mode of data : // If we need use SPIRAM, we should use data cache.Configure the mode of data :
// cache size, cache line size. // cache size, cache line size.
Cache_Suspend_DCache(); Cache_Suspend_DCache();