From 2880ca4ca09368527c2dd509e3d333104acd797b Mon Sep 17 00:00:00 2001
From: Jesse Braham <jesse@beta7.io>
Date: Wed, 12 Oct 2022 09:26:45 -0700
Subject: [PATCH] More corrections to clocks

---
 esp-hal-common/src/clock.rs             | 19 +++++++++++++------
 esp-hal-common/src/clocks_ll/esp32c2.rs | 15 ++-------------
 esp-hal-common/src/rom.rs               |  2 +-
 3 files changed, 16 insertions(+), 20 deletions(-)

diff --git a/esp-hal-common/src/clock.rs b/esp-hal-common/src/clock.rs
index 1715178ce..c67038c69 100644
--- a/esp-hal-common/src/clock.rs
+++ b/esp-hal-common/src/clock.rs
@@ -26,6 +26,9 @@ pub trait Clock {
 #[derive(Debug, Clone, Copy)]
 pub enum CpuClock {
     Clock80MHz,
+    #[cfg(esp32c2)]
+    Clock120MHz,
+    #[cfg(not(esp32c2))]
     Clock160MHz,
     #[cfg(not(any(esp32c2, esp32c3)))]
     Clock240MHz,
@@ -36,6 +39,9 @@ impl Clock for CpuClock {
     fn frequency(&self) -> HertzU32 {
         match self {
             CpuClock::Clock80MHz => HertzU32::MHz(80),
+            #[cfg(esp32c2)]
+            CpuClock::Clock120MHz => HertzU32::MHz(120),
+            #[cfg(not(esp32c2))]
             CpuClock::Clock160MHz => HertzU32::MHz(160),
             #[cfg(not(any(esp32c2, esp32c3)))]
             CpuClock::Clock240MHz => HertzU32::MHz(240),
@@ -46,26 +52,26 @@ impl Clock for CpuClock {
 #[allow(unused)]
 #[derive(Debug, Clone, Copy)]
 pub(crate) enum XtalClock {
-    RtcXtalFreq40M,
-    #[cfg(any(esp32, esp32c2))]
-    RtcXtalFreq26M,
     #[cfg(esp32)]
     RtcXtalFreq24M,
+    #[cfg(any(esp32, esp32c2))]
+    RtcXtalFreq26M,
     #[cfg(any(esp32c3, esp32s3))]
     RtcXtalFreq32M,
+    RtcXtalFreq40M,
     RtcXtalFreqOther(u32),
 }
 
 impl Clock for XtalClock {
     fn frequency(&self) -> HertzU32 {
         match self {
-            XtalClock::RtcXtalFreq40M => HertzU32::MHz(40),
-            #[cfg(any(esp32, esp32c2))]
-            XtalClock::RtcXtalFreq26M => HertzU32::MHz(26),
             #[cfg(esp32)]
             XtalClock::RtcXtalFreq24M => HertzU32::MHz(24),
+            #[cfg(any(esp32, esp32c2))]
+            XtalClock::RtcXtalFreq26M => HertzU32::MHz(26),
             #[cfg(any(esp32c3, esp32s3))]
             XtalClock::RtcXtalFreq32M => HertzU32::MHz(32),
+            XtalClock::RtcXtalFreq40M => HertzU32::MHz(40),
             XtalClock::RtcXtalFreqOther(mhz) => HertzU32::MHz(*mhz),
         }
     }
@@ -74,6 +80,7 @@ impl Clock for XtalClock {
 #[allow(unused)]
 #[derive(Debug, Clone, Copy)]
 pub(crate) enum PllClock {
+    #[cfg(not(esp32c2))]
     Pll320MHz,
     Pll480MHz,
 }
diff --git a/esp-hal-common/src/clocks_ll/esp32c2.rs b/esp-hal-common/src/clocks_ll/esp32c2.rs
index 8adb31c3f..4a9deb461 100644
--- a/esp-hal-common/src/clocks_ll/esp32c2.rs
+++ b/esp-hal-common/src/clocks_ll/esp32c2.rs
@@ -74,16 +74,6 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
 
         // Configure 480M PLL
         match xtal_freq {
-            XtalClock::RtcXtalFreq40M => {
-                div_ref = 0;
-                div7_0 = 8;
-                dr1 = 0;
-                dr3 = 0;
-                dchgp = 5;
-                dcur = 3;
-                dbias = 2;
-            }
-
             XtalClock::RtcXtalFreq26M => {
                 div_ref = 12;
                 div7_0 = 236;
@@ -93,8 +83,7 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
                 dcur = 0;
                 dbias = 2;
             }
-
-            XtalClock::RtcXtalFreqOther(_) => {
+            XtalClock::RtcXtalFreq40M | XtalClock::RtcXtalFreqOther(_) => {
                 div_ref = 0;
                 div7_0 = 8;
                 dr1 = 0;
@@ -172,7 +161,7 @@ pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
         system_control.cpu_per_conf.modify(|_, w| {
             w.cpuperiod_sel().bits(match cpu_clock_speed {
                 CpuClock::Clock80MHz => 0,
-                CpuClock::Clock160MHz => 1,
+                CpuClock::Clock120MHz => 1,
             })
         });
         ets_update_cpu_frequency(cpu_clock_speed.mhz());
diff --git a/esp-hal-common/src/rom.rs b/esp-hal-common/src/rom.rs
index dc44dadec..9c06492fa 100644
--- a/esp-hal-common/src/rom.rs
+++ b/esp-hal-common/src/rom.rs
@@ -6,7 +6,7 @@ pub unsafe fn esp_rom_delay_us(us: u32) {
     #[cfg(esp32)]
     const ESP_ROM_DELAY_US: u32 = 0x4000_8534;
     #[cfg(esp32c2)]
-    const ESP_ROM_DELAY_US: u32 = 0x4000_0050;
+    const ESP_ROM_DELAY_US: u32 = 0x4000_0044;
     #[cfg(esp32c3)]
     const ESP_ROM_DELAY_US: u32 = 0x4000_0050;
     #[cfg(esp32s2)]