Merge pull request #559 from BryanKadzban/add-dma-poll

Add a fn to poll a DMA transfer
This commit is contained in:
Björn Quentin 2023-05-25 09:57:55 +02:00 committed by GitHub
commit 278ce406b6
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10 changed files with 69 additions and 0 deletions

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@ -27,6 +27,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Add some miscellaneous examples for the ESP32-H2 (#548)
- Add initial support for PCNT in ESP32-H2 (#551)
- Add initial support for RMT in ESP32-H2 (#556)
- Add a fn to poll DMA transfers
### Fixed

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@ -846,6 +846,8 @@ where
pub trait DmaTransfer<B, T>: Drop {
/// Wait for the transfer to finish.
fn wait(self) -> (B, T);
/// Check if the transfer is finished.
fn is_done(&self) -> bool;
}
/// Trait to be implemented for an in progress dma transfer.
@ -853,6 +855,8 @@ pub trait DmaTransfer<B, T>: Drop {
pub trait DmaTransferRxTx<BR, BT, T>: Drop {
/// Wait for the transfer to finish.
fn wait(self) -> (BR, BT, T);
/// Check if the transfer is finished.
fn is_done(&self) -> bool;
}
#[cfg(feature = "async")]

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@ -326,6 +326,11 @@ where
(buffer, payload)
}
}
/// Check if the DMA transfer is complete
fn is_done(&self) -> bool {
self.i2s_tx.tx_channel.is_done()
}
}
impl<'d, T, P, TX, BUFFER> Drop for I2sWriteDmaTransfer<T, P, TX, BUFFER>
@ -451,6 +456,11 @@ where
(buffer, payload)
}
}
/// Check if the DMA transfer is complete
fn is_done(&self) -> bool {
self.i2s_rx.rx_channel.is_done()
}
}
impl<T, P, RX, BUFFER> Drop for I2sReadDmaTransfer<T, P, RX, BUFFER>

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@ -861,6 +861,12 @@ pub mod dma {
(rbuffer, tbuffer, payload)
}
}
/// Check if the DMA transfer is complete
fn is_done(&self) -> bool {
let ch = &self.spi_dma.channel;
ch.tx.is_done() && ch.rx.is_done()
}
}
impl<'d, T, TX, RX, P, RXBUF, TXBUF, M> Drop
@ -918,6 +924,12 @@ pub mod dma {
(buffer, payload)
}
}
/// Check if the DMA transfer is complete
fn is_done(&self) -> bool {
let ch = &self.spi_dma.channel;
ch.tx.is_done() && ch.rx.is_done()
}
}
impl<'d, T, TX, RX, P, BUFFER, M> Drop for SpiDmaTransfer<'d, T, TX, RX, P, BUFFER, M>

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@ -98,6 +98,13 @@ fn main() -> ! {
let transfer = spi.dma_transfer(send, receive).unwrap();
// here we could do something else while DMA transfer is in progress
let mut i = 0;
// Check is_done until the transfer is almost done (32000 bytes at 100kHz is
// 2.56 seconds), then move to wait().
while !transfer.is_done() && i < 10 {
delay.delay_ms(250u32);
i += 1;
}
// the buffers and spi is moved into the transfer and we can get it back via
// `wait`
(receive, send, spi) = transfer.wait();

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@ -99,6 +99,13 @@ fn main() -> ! {
let transfer = spi.dma_transfer(send, receive).unwrap();
// here we could do something else while DMA transfer is in progress
let mut i = 0;
// Check is_done until the transfer is almost done (32000 bytes at 100kHz is
// 2.56 seconds), then move to wait().
while !transfer.is_done() && i < 10 {
delay.delay_ms(250u32);
i += 1;
}
// the buffers and spi is moved into the transfer and we can get it back via
// `wait`
(receive, send, spi) = transfer.wait();

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@ -106,6 +106,13 @@ fn main() -> ! {
let transfer = spi.dma_transfer(send, receive).unwrap();
// here we could do something else while DMA transfer is in progress
let mut i = 0;
// Check is_done until the transfer is almost done (32000 bytes at 100kHz is
// 2.56 seconds), then move to wait().
while !transfer.is_done() && i < 10 {
delay.delay_ms(250u32);
i += 1;
}
// the buffers and spi is moved into the transfer and we can get it back via
// `wait`
(receive, send, spi) = transfer.wait();

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@ -107,6 +107,13 @@ fn main() -> ! {
let transfer = spi.dma_transfer(send, receive).unwrap();
// here we could do something else while DMA transfer is in progress
let mut i = 0;
// Check is_done until the transfer is almost done (32000 bytes at 100kHz is
// 2.56 seconds), then move to wait().
while !transfer.is_done() && i < 10 {
delay.delay_ms(250u32);
i += 1;
}
// the buffers and spi is moved into the transfer and we can get it back via
// `wait`
(receive, send, spi) = transfer.wait();

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@ -98,6 +98,13 @@ fn main() -> ! {
let transfer = spi.dma_transfer(send, receive).unwrap();
// here we could do something else while DMA transfer is in progress
let mut i = 0;
// Check is_done until the transfer is almost done (32000 bytes at 100kHz is
// 2.56 seconds), then move to wait().
while !transfer.is_done() && i < 10 {
delay.delay_ms(250u32);
i += 1;
}
// the buffers and spi is moved into the transfer and we can get it back via
// `wait`
(receive, send, spi) = transfer.wait();

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@ -106,6 +106,13 @@ fn main() -> ! {
let transfer = spi.dma_transfer(send, receive).unwrap();
// here we could do something else while DMA transfer is in progress
let mut i = 0;
// Check is_done until the transfer is almost done (32000 bytes at 100kHz is
// 2.56 seconds), then move to wait().
while !transfer.is_done() && i < 10 {
delay.delay_ms(250u32);
i += 1;
}
// the buffers and spi is moved into the transfer and we can get it back via
// `wait`
(receive, send, spi) = transfer.wait();