Enable I2S tests on ESP32 and work around first sample issue (#2194)
* Enable I2S tests on ESP32 and work around first sample issue * Fix sample->channel assignment inconsistency * Add to changelog
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@ -57,6 +57,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- Fix I2C ending up in a state when only re-creating the peripheral makes it useable again (#2141)
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- Fix `SpiBus::transfer` transferring data twice in some cases (#2159)
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- Fixed UART freezing when using `RcFast` clock source on ESP32-C2/C3 (#2170)
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- I2S: on ESP32 and ESP32-S2 data is now output to the right (WS=1) channel first. (#2194)
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### Removed
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@ -1137,10 +1137,15 @@ mod private {
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// Short frame synchronization
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w.tx_short_sync().bit(false);
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w.rx_short_sync().bit(false);
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w.tx_msb_right().clear_bit();
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w.rx_msb_right().clear_bit();
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w.tx_right_first().clear_bit();
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w.rx_right_first().clear_bit();
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// Send MSB to the right channel to be consistent with ESP32-S3 et al.
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w.tx_msb_right().set_bit();
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w.rx_msb_right().set_bit();
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// ESP32 generates two clock pulses first. If the WS is low, those first clock
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// pulses are indistinguishable from real data, which corrupts the first few
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// samples. So we send the right channel first (which means WS is high during
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// the first sample) to prevent this issue.
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w.tx_right_first().set_bit();
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w.rx_right_first().set_bit();
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w.tx_mono().clear_bit();
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w.rx_mono().clear_bit();
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w.sig_loopback().clear_bit()
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@ -51,11 +51,9 @@ macro_rules! common_test_pins {
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cfg_if::cfg_if! {
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if #[cfg(any(esp32s2, esp32s3))] {
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($io.pins.gpio9, $io.pins.gpio10)
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}
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else if #[cfg(esp32)] {
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} else if #[cfg(esp32)] {
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($io.pins.gpio26, $io.pins.gpio27)
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}
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else {
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} else {
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($io.pins.gpio2, $io.pins.gpio3)
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}
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}
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@ -3,7 +3,7 @@
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//! This test uses I2S TX to transmit known data to I2S RX (forced to slave mode
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//! with loopback mode enabled).
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//% CHIPS: esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: generic-queue
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#![no_std]
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