Change target_arch cfgs to chip features
This hopefully will allow the documentation's build to succeed on docs.rs, as it uses the `x86_64-unknown-linux-gnu` target by default
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@ -17,7 +17,7 @@
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//! [esp32s3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s3-hal
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#![no_std]
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#![cfg_attr(target_arch = "xtensa", feature(asm_experimental_arch))]
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#![cfg_attr(not(feature = "esp32c3"), feature(asm_experimental_arch))]
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#[cfg(feature = "esp32")]
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pub use esp32 as pac;
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@ -38,8 +38,8 @@ pub mod efuse;
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pub mod gpio;
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pub mod i2c;
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#[cfg_attr(target_arch = "riscv32", path = "interrupt/riscv.rs")]
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#[cfg_attr(target_arch = "xtensa", path = "interrupt/xtensa.rs")]
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#[cfg_attr(feature = "esp32c3", path = "interrupt/riscv.rs")]
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#[cfg_attr(not(feature = "esp32c3"), path = "interrupt/xtensa.rs")]
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pub mod interrupt;
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pub mod ledc;
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pub mod prelude;
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@ -90,12 +90,13 @@ pub enum Cpu {
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}
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pub fn get_core() -> Cpu {
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#[cfg(all(target_arch = "xtensa", feature = "multi_core"))]
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#[cfg(all(not(feature = "esp32c3"), feature = "multi_core"))]
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match ((xtensa_lx::get_processor_id() >> 13) & 1) != 0 {
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false => Cpu::ProCpu,
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true => Cpu::AppCpu,
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}
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// #[cfg(all(target_arch = "riscv32", feature = "multi_core"))]
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// #[cfg(all(feature = "esp32c3", feature = "multi_core"))]
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// TODO get hart_id
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// single core always has ProCpu only
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@ -108,7 +109,7 @@ mod critical_section_impl {
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critical_section::set_impl!(CriticalSection);
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#[cfg(target_arch = "xtensa")]
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#[cfg(not(feature = "esp32c3"))]
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mod xtensa {
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unsafe impl critical_section::Impl for super::CriticalSection {
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@ -139,7 +140,7 @@ mod critical_section_impl {
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}
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}
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#[cfg(target_arch = "riscv32")]
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#[cfg(feature = "esp32c3")]
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mod riscv {
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unsafe impl critical_section::Impl for super::CriticalSection {
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unsafe fn acquire() -> critical_section::RawRestoreState {
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