diff --git a/esp-hal-common/src/serial.rs b/esp-hal-common/src/serial.rs index c484526d3..aba937d0a 100644 --- a/esp-hal-common/src/serial.rs +++ b/esp-hal-common/src/serial.rs @@ -6,11 +6,9 @@ use crate::pac::{uart0::RegisterBlock, UART0, UART1}; const UART_FIFO_SIZE: u16 = 128; -/// UART-specific errors #[derive(Debug)] pub enum Error {} -/// UART peripheral (UART) pub struct Serial { uart: T, } @@ -26,13 +24,10 @@ impl Serial { } pub trait Instance { - /// Return registerblock of uart instance as if it were UART0 - fn as_uart0(&self) -> &RegisterBlock; + fn register_block(&self) -> &RegisterBlock; - /// Clear and disable all tx-related interrupts fn disable_tx_interrupts(&mut self) { - // Disable UART TX interrupts - self.as_uart0().int_clr.write(|w| { + self.register_block().int_clr.write(|w| { w.txfifo_empty_int_clr() .set_bit() .tx_brk_done_int_clr() @@ -43,7 +38,7 @@ pub trait Instance { .set_bit() }); - self.as_uart0().int_ena.write(|w| { + self.register_block().int_ena.write(|w| { w.txfifo_empty_int_ena() .clear_bit() .tx_brk_done_int_ena() @@ -55,10 +50,8 @@ pub trait Instance { }); } - /// Clear and disable all rx-related interrupts fn disable_rx_interrupts(&mut self) { - // Disable UART RX interrupts - self.as_uart0().int_clr.write(|w| { + self.register_block().int_clr.write(|w| { w.rxfifo_full_int_clr() .set_bit() .rxfifo_ovf_int_clr() @@ -67,7 +60,7 @@ pub trait Instance { .set_bit() }); - self.as_uart0().int_ena.write(|w| { + self.register_block().int_ena.write(|w| { w.rxfifo_full_int_ena() .clear_bit() .rxfifo_ovf_int_ena() @@ -77,63 +70,66 @@ pub trait Instance { }); } - /// Get the number of occupied entries in the tx fifo buffer fn get_tx_fifo_count(&mut self) -> u16 { - self.as_uart0().status.read().txfifo_cnt().bits().into() + self.register_block() + .status + .read() + .txfifo_cnt() + .bits() + .into() } - /// Get the number of occupied entries in the rx fifo buffer fn get_rx_fifo_count(&mut self) -> u16 { - self.as_uart0().status.read().rxfifo_cnt().bits().into() + self.register_block() + .status + .read() + .rxfifo_cnt() + .bits() + .into() } - /// Check if the UART TX statemachine is is idle fn is_tx_idle(&mut self) -> bool { #[cfg(feature = "32")] - let ret = self.as_uart0().status.read().st_utx_out().bits() == 0x0u8; + let idle = self.register_block().status.read().st_utx_out().bits() == 0x0u8; #[cfg(not(feature = "32"))] - let ret = self.as_uart0().fsm_status.read().st_utx_out().bits() == 0x0u8; + let idle = self.register_block().fsm_status.read().st_utx_out().bits() == 0x0u8; - ret + idle } - /// Check if the UART RX statemachine is is idle fn is_rx_idle(&mut self) -> bool { #[cfg(feature = "32")] - let ret = self.as_uart0().status.read().st_urx_out().bits() == 0x0u8; + let idle = self.register_block().status.read().st_urx_out().bits() == 0x0u8; #[cfg(not(feature = "32"))] - let ret = self.as_uart0().fsm_status.read().st_urx_out().bits() == 0x0u8; + let idle = self.register_block().fsm_status.read().st_urx_out().bits() == 0x0u8; - ret + idle } } -/// Write half of a serial interface impl Write for Serial { type Error = Error; - /// Writes a single word to the serial interface fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { - if self.uart.get_tx_fifo_count() >= UART_FIFO_SIZE { - Err(nb::Error::WouldBlock) - } else { + if self.uart.get_tx_fifo_count() < UART_FIFO_SIZE { #[cfg(feature = "32")] self.uart - .as_uart0() + .register_block() .fifo() .write(|w| unsafe { w.rxfifo_rd_byte().bits(word) }); #[cfg(not(feature = "32"))] self.uart - .as_uart0() + .register_block() .fifo .write(|w| unsafe { w.rxfifo_rd_byte().bits(word) }); Ok(()) + } else { + Err(nb::Error::WouldBlock) } } - /// Ensures that none of the previously written words are still buffered fn flush(&mut self) -> nb::Result<(), Self::Error> { if self.uart.is_tx_idle() { Ok(()) @@ -143,17 +139,28 @@ impl Write for Serial { } } -/// Write half of a serial interface impl Read for Serial { type Error = Error; - /// Reads a single word from the serial interface fn read(&mut self) -> nb::Result { if self.uart.get_rx_fifo_count() > 0 { #[cfg(feature = "32")] - let value = self.uart.as_uart0().fifo().read().rxfifo_rd_byte().bits(); + let value = self + .uart + .register_block() + .fifo() + .read() + .rxfifo_rd_byte() + .bits(); + #[cfg(not(feature = "32"))] - let value = self.uart.as_uart0().fifo.read().rxfifo_rd_byte().bits(); + let value = self + .uart + .register_block() + .fifo + .read() + .rxfifo_rd_byte() + .bits(); Ok(value) } else { @@ -171,27 +178,24 @@ impl core::fmt::Write for Serial { } } -/// Specific instance implementation for the UART0 peripheral impl Instance for UART0 { #[inline(always)] - fn as_uart0(&self) -> &RegisterBlock { + fn register_block(&self) -> &RegisterBlock { self } } -/// Specific instance implementation for the UART1 peripheral impl Instance for UART1 { #[inline(always)] - fn as_uart0(&self) -> &RegisterBlock { + fn register_block(&self) -> &RegisterBlock { self } } #[cfg(any(feature = "32", feature = "32s3"))] -/// Specific instance implementation for the UART2 peripheral impl Instance for UART2 { #[inline(always)] - fn as_uart0(&self) -> &RegisterBlock { + fn register_block(&self) -> &RegisterBlock { self } } diff --git a/esp-hal-common/src/timer.rs b/esp-hal-common/src/timer.rs index 4b66f68c0..1a6c4ebb4 100644 --- a/esp-hal-common/src/timer.rs +++ b/esp-hal-common/src/timer.rs @@ -11,13 +11,8 @@ pub struct Timer { } pub enum Error { - /// Report that the timer is active and certain management - /// operations cannot be performed safely TimerActive, - /// Report that the timer is inactive and thus not - /// ever reaching any potentially configured alarm value TimerInactive, - /// Report that the alarm functionality is disabled AlarmInactive, } @@ -31,48 +26,56 @@ where } pub trait Instance { - fn as_timg0(&self) -> &RegisterBlock; + fn register_block(&self) -> &RegisterBlock; fn reset_counter(&mut self) { - let reg_block = self.as_timg0(); + let reg_block = self.register_block(); reg_block .t0loadlo .write(|w| unsafe { w.t0_load_lo().bits(0) }); + reg_block .t0loadhi .write(|w| unsafe { w.t0_load_hi().bits(0) }); + reg_block.t0load.write(|w| unsafe { w.t0_load().bits(1) }); } fn set_counter_active(&mut self, state: bool) { - self.as_timg0().t0config.modify(|_, w| w.t0_en().bit(state)); + self.register_block() + .t0config + .modify(|_, w| w.t0_en().bit(state)); } fn is_counter_active(&mut self) -> bool { - self.as_timg0().t0config.read().t0_en().bit_is_set() + self.register_block().t0config.read().t0_en().bit_is_set() } fn set_counter_decrementing(&mut self, decrementing: bool) { - self.as_timg0() + self.register_block() .t0config .modify(|_, w| w.t0_increase().bit(!decrementing)); } fn set_auto_reload(&mut self, auto_reload: bool) { - self.as_timg0() + self.register_block() .t0config .modify(|_, w| w.t0_autoreload().bit(auto_reload)); } fn set_alarm_active(&mut self, state: bool) { - self.as_timg0() + self.register_block() .t0config .modify(|_, w| w.t0_alarm_en().bit(state)); } fn is_alarm_active(&mut self) -> bool { - self.as_timg0().t0config.read().t0_alarm_en().bit_is_set() + self.register_block() + .t0config + .read() + .t0_alarm_en() + .bit_is_set() } fn load_alarm_value(&mut self, value: u64) { @@ -80,23 +83,26 @@ pub trait Instance { let high = (value >> 32) as u32; let low = (value & 0xFFFF_FFFF) as u32; - let reg_block = self.as_timg0(); + let reg_block = self.register_block(); reg_block .t0alarmlo .write(|w| unsafe { w.t0_alarm_lo().bits(low) }); + reg_block .t0alarmhi .write(|w| unsafe { w.t0_alarm_hi().bits(high) }); } fn set_wdt_enabled(&mut self, enabled: bool) { - let reg_block = self.as_timg0(); + let reg_block = self.register_block(); reg_block .wdtwprotect .write(|w| unsafe { w.wdt_wkey().bits(0u32) }); + reg_block.wdtconfig0.write(|w| w.wdt_en().bit(enabled)); + reg_block .wdtwprotect .write(|w| unsafe { w.wdt_wkey().bits(0x50D8_3AA1u32) }); @@ -130,31 +136,19 @@ where panic!("Called wait on an inactive timer!"); } - let int_raw_is_clear = self - .timg - .as_timg0() - .int_raw_timers - .read() - .t0_int_raw() - .bit_is_clear(); - - if int_raw_is_clear { - Err(nb::Error::WouldBlock) - } else { - self.timg - .as_timg0() - .int_clr_timers - .write(|w| w.t0_int_clr().set_bit()); + let reg_block = self.timg.register_block(); + if reg_block.int_raw_timers.read().t0_int_raw().bit_is_set() { + reg_block.int_clr_timers.write(|w| w.t0_int_clr().set_bit()); self.timg.set_alarm_active(true); Ok(()) + } else { + Err(nb::Error::WouldBlock) } } } -impl Periodic for Timer where T: Instance {} - impl Cancel for Timer where T: Instance, @@ -174,6 +168,8 @@ where } } +impl Periodic for Timer where T: Instance {} + impl WatchdogDisable for Timer where T: Instance, @@ -185,14 +181,14 @@ where impl Instance for TIMG0 { #[inline(always)] - fn as_timg0(&self) -> &RegisterBlock { + fn register_block(&self) -> &RegisterBlock { self } } impl Instance for TIMG1 { #[inline(always)] - fn as_timg0(&self) -> &RegisterBlock { + fn register_block(&self) -> &RegisterBlock { self } } diff --git a/rustfmt.toml b/rustfmt.toml index 5fe7c4b95..d377e8b8f 100644 --- a/rustfmt.toml +++ b/rustfmt.toml @@ -1,4 +1,5 @@ edition = "2018" +enum_discrim_align_threshold = 15 group_imports = "StdExternalCrate" imports_granularity = "Crate" imports_layout = "HorizontalVertical"